CoreSF2Config |
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Overview
CoreSF2Config facilitates the configuration of peripheral blocks in a SmartFusion®2 device, including the microcontroller subsystem (MSS) double data rate (DDR) controller, known as the MDDR, fabric DDR (FDDR) controller, and high speed serial interface blocks (SERDESIF). CoreSF2Config has a mirrored master advanced peripheral bus (APB) port and several mirrored slave APB ports. The mirrored master APB port should be connected to the FIC_2_APB_MASTER master port of MSS and the mirrored slave APB ports should be connected to the APB slave ports of the blocks that need to be configured.
Key Features:
Supported Devices:
Market Segments:
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Alphanumeric Parameter | Value |
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Core Provider | Microchip |
Functional Category | |
Device Family | SmartFusion2 |
Application | 1588 Timing Card,Aerospace,Automotive,Carrier,Computer,Connected Home,Consumer,Data Communications,Gaming,Industrial,IP Camera,IP Phone,Line Card,Medical,Microprocessor,Military,Multimedia,Portable,Signal Processing,SMB,Storage,SyncE Timing Card,Telecom,USB Audio,Wireless,WiMax |
This part can be found in the following product categories: