CoreSDR_AXI |
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Overview
CoreSDR_AXI is intended to provide a 64-bit advanced microcontroller bus architecture (AMBA®) advanced extensible interface (AXI) to an external single data rate (SDR) synchronous dynamic random access memory (SDRAM). The design consists of an AXI controller, read and write data buffers, and a single instantiation of CoreSDR, which contains a generic CPU interface. Key Features:
Supported Devices:
Market Segments:
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Alphanumeric Parameter | Value |
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Core Provider | Microchip |
Functional Category | Memory Controllers |
Device Family | SmartFusion2 |
Application | 1588 Timing Card,Aerospace,Automotive,Carrier,Computer,Connected Home,Consumer,Data Communications,Gaming,Industrial,IP Camera,IP Phone,Line Card,Medical,Microprocessor,Military,Multimedia,Portable,Signal Processing,SMB,Storage,SyncE Timing Card,Telecom,USB Audio,Wireless,WiMax |
This part can be found in the following product categories: