CoreConfigP |
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Overview
CoreConfigP facilitates the configuration of peripheral blocks in a SmartFusion®2 or IGLOO®2 device. The blocks of interest are the double data rate (DDR) memory controllers and the high speed serial interface blocks (SERDESIF). CoreConfigP has a mirrored master advanced peripheral bus (APB) port and several mirrored slave APB ports. The mirrored master APB port should be connected to the FIC_2_APB_MASTER master port of the microcontroller subsystem (MSS) in the case of SmartFusion2, or the high performance memory subsystem (HPMS) in the case of IGLOO2. The mirrored slave APB ports should be connected to the APB slave ports of the blocks that need to be configured. Key Features:
Supported Devices:
Market Segments:
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Alphanumeric Parameter | Value |
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Core Provider | Microchip |
Functional Category | Processors & Peripherals |
Device Family | IGLOO2,SmartFusion2 |
Application | 1588 Timing Card,Aerospace,Automotive,Carrier,Computer,Connected Home,Consumer,Data Communications,Gaming,Industrial,IP Camera,IP Phone,Line Card,Medical,Microprocessor,Military,Multimedia,Portable,Signal Processing,SMB,Storage,SyncE Timing Card,Telecom,USB Audio,Wireless,WiMax |
This part can be found in the following product categories: