CoreAPBSRAM |
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Overview
CoreAPBSRAM provides an APB bus interface to the embedded SRAM memory blocks within Microsemi's Flash devices. In these devices, software running on an APB-based microprocessor will be able to read and write the embedded SRAM. CoreAPBSRAM implements a standard Slave APB Bus 32-bit hardware interface. The core supports the ability to logically merge multiple SRAM blocks into one large area of SRAM. Features:
Supported Devices:
Market Segments:
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Alphanumeric Parameter | Value |
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Core Provider | Microchip |
Functional Category | Bus Interfaces,Memory Controllers,Processors & Peripherals |
Device Family | IGLOO,ProASIC3 nano,IGLOO nano,ProASIC3L,RT ProASIC3,IGLOO PLUS,SmartFusion2,SmartFusion,ProASIC3,Fusion |
Application | 1588 Timing Card,Aerospace,Automotive,Carrier,Computer,Connected Home,Consumer,Data Communications,Gaming,Industrial,IP Camera,IP Phone,Line Card,Medical,Microprocessor,Military,Multimedia,Portable,Signal Processing,SMB,Storage,SyncE Timing Card,Telecom,USB Audio,Wireless,WiMax |
This part can be found in the following product categories: