-- =================================================================== -- $Id: $ -- =================================================================== -- Copyright (c) 2012 Microsemi Corporation -- All Rights Reserved. -- -- THIS MATERIAL IS CONSIDERED PROPRIETARY BY -- MICROSEMI CORPORATION. UNAUTHORIZED ACCESS OR USE IS PROHIBITED. -- =================================================================== -- $RCSfile: $ -- -- $Author: $ -- =================================================================== -- -- Abstract : -- -- Detail : -- -- Usage : -- -- File usage : -- Script name: "/design/telecom/DS31IP38/users/release/design/scripts/create_jtag_and_pads", Version 1.91 -- (This script is maintained in /design/telecom/DS31IP38/users/release) -- BSDL Script name: "/design/telecom/DS31IP38/users/release/design/scripts/bsdl.pm", Version 1.35, Wed Nov 28 14:21:36 2007 -- (This script is maintained in /design/telecom/DS31IP38/users/release) -- Library name:"/design/telecom/DS31IP38/users/release/design/scripts/library.tsmc_18.pm", Version 1.115 -- Pindef file: "hq90_bsdl.pindef", Version unknown -- -- -- -- This file was script-generated. -- -- =================================================================== -- =================================================================== -- BSDL file for design MAX24305 -- Created by DS31IP38 JTAG generator -- Date: -- *********************************************************************** entity MAX24305 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "CSBGA_81"); -- This section declares all the ports in the design. port ( CS_N : inout bit; NC : linkage bit_vector (0 to 3); GPIO1 : inout bit; GPIO2 : inout bit; GPIO3 : inout bit; GPIO4 : inout bit; IC1NEG : linkage bit; IC1POS : linkage bit; IC2NEG : linkage bit; IC2POS : linkage bit; JTCLK : in bit; JTDI : in bit; JTDO : out bit; JTMS : in bit; JTRST_N : in bit; MCLKOSCN : linkage bit; MCLKOSCP : linkage bit; OC10NEG : linkage bit; OC10POS : linkage bit; OC1NEG : linkage bit; OC1POS : linkage bit; OC2NEG : linkage bit; OC2POS : linkage bit; OC3NEG : linkage bit; OC3POS : linkage bit; OC8NEG : linkage bit; OC8POS : linkage bit; RST_N : inout bit; SCLK : inout bit; SDI : inout bit; SDO : inout bit; TEST : inout bit; VD33 : linkage bit; VDDO18A : linkage bit; VDDO18B : linkage bit; VDDO18C : linkage bit; VDDO18D : linkage bit; VDDOA : linkage bit; VDDOB : linkage bit; VDDOC : linkage bit; VDDOD : linkage bit; VDD_18 : linkage bit; VDD_APLL1_18 : linkage bit; VDD_APLL1_33 : linkage bit; VDD_APLL2_18 : linkage bit; VDD_APLL2_33 : linkage bit; VDD_DIG_18 : linkage bit_vector (0 to 1); VDD_OC_18 : linkage bit; VDD_XO_18 : linkage bit; VDD_XO_33 : linkage bit; VSSOA : linkage bit; VSSOB : linkage bit_vector (0 to 1); VSSOC : linkage bit_vector (0 to 1); VSSOD : linkage bit; VSS_APLL1 : linkage bit_vector (0 to 1); VSS_APLL2 : linkage bit_vector (0 to 1); VSS_DIG : linkage bit_vector (0 to 1); VSS_OC : linkage bit; VSS_XO : linkage bit; VSUB : linkage bit; XIN : linkage bit; XOUT : linkage bit ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of MAX24305: entity is "STD_1149_1_1993"; attribute PIN_MAP of MAX24305: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant CSBGA_81: PIN_MAP_STRING := "CS_N : B7," & "NC : (C3,A4,B4,C4)," & "GPIO1 : A8," & "GPIO2 : B8," & "GPIO3 : A2," & "GPIO4 : B2," & "IC1NEG : B9," & "IC1POS : A9," & "IC2NEG : B1," & "IC2POS : A1," & "JTCLK : B5," & "JTDI : C5," & "JTDO : B6," & "JTMS : C7," & "JTRST_N : C6," & "MCLKOSCN : B3," & "MCLKOSCP : A3," & "OC10NEG : E2," & "OC10POS : E1," & "OC1NEG : E8," & "OC1POS : E9," & "OC2NEG : F8," & "OC2POS : F9," & "OC3NEG : H9," & "OC3POS : J9," & "OC8NEG : H1," & "OC8POS : J1," & "RST_N : C8," & "SCLK : A6," & "SDI : A7," & "SDO : A5," & "TEST : C2," & "VD33 : D7," & "VDDO18A : C9," & "VDDO18B : H6," & "VDDO18C : H4," & "VDDO18D : C1," & "VDDOA : D8," & "VDDOB : G8," & "VDDOC : G2," & "VDDOD : D2," & "VDD_18 : D6," & "VDD_APLL1_18 : E6," & "VDD_APLL1_33 : E7," & "VDD_APLL2_18 : E4," & "VDD_APLL2_33 : E3," & "VDD_DIG_18 : (D4,E5)," & "VDD_OC_18 : G3," & "VDD_XO_18 : G5," & "VDD_XO_33 : G6," & "VSSOA : D9," & "VSSOB : (G9,J6)," & "VSSOC : (G1,J4)," & "VSSOD : D1," & "VSS_APLL1 : (F6,F7)," & "VSS_APLL2 : (F3,F4)," & "VSS_DIG : (D5,F5)," & "VSS_OC : G4," & "VSS_XO : G7," & "VSUB : D3," & "XIN : H5," & "XOUT : J5 " ; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST_N : signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of MAX24305: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of MAX24305: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "USER1 (101)," & "USER2 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of MAX24305: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of MAX24305: entity is "0000" & -- 4-bit version number "0000000011000010" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of MAX24305: entity is "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of MAX24305: entity is 28; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of MAX24305: entity is -- -- num cell port function safe [ccell disval rslt] -- "27 (BC_1, *, controlr, 0), " & "26 (BC_0, GPIO1, bidir, X, 27 , 0, Z), " & "25 (BC_1, *, controlr, 0), " & "24 (BC_0, GPIO2, bidir, X, 25 , 0, Z), " & "23 (BC_1, *, controlr, 0), " & "22 (BC_0, RST_N, bidir, X, 23 , 0, Z), " & "21 (BC_1, *, controlr, 0), " & "20 (BC_0, CS_N, bidir, X, 21 , 0, Z), " & "19 (BC_1, *, controlr, 0), " & "18 (BC_0, SCLK, bidir, X, 19 , 0, Z), " & "17 (BC_1, *, controlr, 0), " & "16 (BC_0, SDI, bidir, X, 17 , 0, Z), " & "15 (BC_1, *, controlr, 0), " & "14 (BC_0, SDO, bidir, X, 15 , 0, Z), " & "13 (BC_0, *, internal, 0), " & "12 (BC_0, *, internal, X), " & "11 (BC_1, *, internal, 0), " & "10 (BC_0, *, internal, X), " & "9 (BC_1, *, internal, 0), " & "8 (BC_0, *, internal, X), " & "7 (BC_1, *, internal, 0), " & "6 (BC_0, *, internal, X), " & "5 (BC_1, *, controlr, 0), " & "4 (BC_0, TEST, bidir, X, 5 , 0, Z), " & "3 (BC_1, *, controlr, 0), " & "2 (BC_0, GPIO3, bidir, X, 3 , 0, Z), " & "1 (BC_1, *, controlr, 0), " & "0 (BC_0, GPIO4, bidir, X, 1 , 0, Z) " ; end MAX24305; -- =================================================================== -- ===================================================================