Project Settings
Project Name EPCS_TX_RX_syn Implementation Name synthesis
Top Module EPCS_TX_RX Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 21 8 0 - 00m:01s - 2/14/2017
11:25:13 AM
(premap)Complete 3 2 0 0m:00s 0m:00s 136MB 2/14/2017
11:25:15 AM
(fpga_mapper)Complete 14 2 0 0m:01s 0m:01s 136MB 2/14/2017
11:25:17 AM
Multi-srs Generator Complete2/14/2017
11:25:14 AM

Area Summary
Carry Cells 33 Sequential Cells 92
DSP Blocks (MACC_PA) (dsp_used) 0 I/O Cells 12
Global Clock Buffers 3 LUTs (total_luts) 90

Timing Summary
Clock NameReq FreqEst FreqSlack
REF_CLK_PAD_P_0156.3 MHzNANA
SD1_0/PF_XCVR_0/LANE0/RX_CLK_G62.5 MHz173.1 MHz10.222
SD1_0/PF_XCVR_0/LANE0/TX_CLK_G62.5 MHz173.1 MHz13.210
SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock100.0 MHz1157.8 MHz9.136
SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|REF_CLK_inferred_clock100.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 4 / 0