#Build: Synplify Pro L-2016.09M-G5, Build 065R, Nov 16 2016 #install: D:\Microsemi\Libero_SoC_PolarFire\SynplifyPro #OS: Windows 7 6.1 #Hostname: W764-ALIM # Tue Feb 14 11:25:12 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_PolarFire\SynplifyPro\lib\generic\acg5.v" (library work) @I::"D:\Microsemi\Libero_SoC_PolarFire\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Microsemi\Libero_SoC_PolarFire\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_PolarFire\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_PolarFire\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\Actel\SgCore\PF_TX_PLL\1.0.100\TX_PLL_syn_comps.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\work\SD1\PF_TX_PLL_0\SD1_PF_TX_PLL_0_PF_TX_PLL.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\Actel\SgCore\PF_XCVR\1.0.210\XCVR_8B10B_syn_comps.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\work\SD1\PF_XCVR_0\SD1_PF_XCVR_0_PF_XCVR.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\Actel\SgCore\PF_XCVR_REF_CLK\1.0.100\XCVR_REF_CLK_syn_comps.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\work\SD1\PF_XCVR_REF_CLK_0\SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\work\SD1\SD1.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\hdl\count_check.v" (library work) @W:CG289 : count_check.v(230) | Specified digits overflow the number's size @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\hdl\count_gen.v" (library work) @I::"D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\component\work\EPCS_TX_RX\EPCS_TX_RX.v" (library work) Verilog syntax check successful! Selecting top level module EPCS_TX_RX @N:CG364 : count_check.v(24) | Synthesizing module count_check in library work. @N:CG179 : count_check.v(182) | Removing redundant assignment. @N:CG179 : count_check.v(219) | Removing redundant assignment. @N:CG179 : count_check.v(220) | Removing redundant assignment. @N:CG179 : count_check.v(221) | Removing redundant assignment. @W:CL113 : count_check.v(105) | Feedback mux created for signal shift. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements. @W:CL250 : count_check.v(105) | All reachable assignments to shift assign 0, register removed by optimization @N:CG364 : count_gen.v(19) | Synthesizing module count_gen in library work. @N:CG364 : acg5.v(504) | Synthesizing module VCC in library work. @N:CG364 : TX_PLL_syn_comps.v(5) | Synthesizing module TX_PLL in library work. @N:CG364 : acg5.v(500) | Synthesizing module GND in library work. @N:CG364 : SD1_PF_TX_PLL_0_PF_TX_PLL.v(5) | Synthesizing module SD1_PF_TX_PLL_0_PF_TX_PLL in library work. @N:CG364 : XCVR_8B10B_syn_comps.v(5) | Synthesizing module XCVR_8B10B in library work. @N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work. @N:CG364 : SD1_PF_XCVR_0_PF_XCVR.v(5) | Synthesizing module SD1_PF_XCVR_0_PF_XCVR in library work. @N:CG364 : XCVR_REF_CLK_syn_comps.v(5) | Synthesizing module XCVR_REF_CLK in library work. @N:CG364 : SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK.v(5) | Synthesizing module SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK in library work. @W:CL168 : SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK.v(27) | Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK.v(26) | Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : SD1.v(9) | Synthesizing module SD1 in library work. @N:CG364 : EPCS_TX_RX.v(9) | Synthesizing module EPCS_TX_RX in library work. @W:CL190 : count_gen.v(70) | Optimizing register bit delay_cnt[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : count_gen.v(70) | Pruning register bit 2 of delay_cnt[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : count_gen.v(70) | Trying to extract state machine for register sm. Extracted state machine for register sm State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @W:CL279 : count_gen.v(70) | Pruning register bits 15 to 8 of data_out[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 14 11:25:13 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 14 11:25:13 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 14 11:25:13 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Feb 14 11:25:14 2017 ###########################################################] Pre-mapping Report # Tue Feb 14 11:25:14 2017 Synopsys Generic Technology Pre-mapping, Version mapact, Build 1925R, Built Nov 24 2016 11:20:54 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-G5 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Reading constraint file: D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\designer\EPCS_TX_RX\synthesis.fdc Linked File: EPCS_TX_RX_scck.rpt Printing clock summary report in "D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\synthesis\EPCS_TX_RX_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) syn_allowed_resources : blockrams=952 set on top level netlist EPCS_TX_RX Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------- REF_CLK_PAD_P_0 156.3 MHz 6.400 declared default_clkgroup 0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G 62.5 MHz 16.000 declared default_clkgroup 51 SD1_0/PF_XCVR_0/LANE0/TX_CLK_G 62.5 MHz 16.000 declared default_clkgroup 31 SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 12 SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|REF_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 2 =========================================================================================================================================== @W:MT530 : sd1_pf_tx_pll_0_pf_tx_pll.v(25) | Found inferred clock SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|REF_CLK_inferred_clock which controls 2 sequential elements including SD1_0.PF_TX_PLL_0.txpll_isnt_0. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : count_check.v(248) | Found inferred clock SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock which controls 12 sequential elements including count_check_0.tx_req_d2. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\synthesis\EPCS_TX_RX.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Encoding state machine sm[4:0] (in view: work.count_gen(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 136MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 14 11:25:15 2017 ###########################################################] Map & Optimize Report # Tue Feb 14 11:25:15 2017 Synopsys Generic Technology Mapper, Version mapact, Build 1925R, Built Nov 24 2016 11:20:54 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-G5 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 104MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) @N:MO231 : count_check.v(105) | Found counter in view:work.count_check(verilog) instance c[7:0] @N:MO231 : count_check.v(171) | Found counter in view:work.count_check(verilog) instance reg_error[5:0] @N:MF179 : count_check.v(133) | Found 16 by 16 bit equality operator ('==') cnt_lock_2 (in view: work.count_check(verilog)) Encoding state machine sm[4:0] (in view: work.count_gen(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 9.09ns 93 / 92 @N:FP130 : | Promoting Net SD1_0_FAB_REF_CLK on CLKINT I_40 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 135MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 4 non-gated/non-generated clock tree(s) driving 95 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =============================================== Non-Gated/Non-Generated Clocks ================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------------------- ClockId0001 SD1_0.PF_XCVR_REF_CLK_0.I_IO XCVR_REF_CLK 12 count_check_0.tx_req_d2 ClockId0002 SD1_0.PF_XCVR_REF_CLK_0.I_IO XCVR_REF_CLK 1 SD1_0.PF_TX_PLL_0.txpll_isnt_0 ClockId0003 SD1_0.PF_XCVR_0.LANE0 clock definition on XCVR_8B10B 51 SD1_0.PF_XCVR_0.LANE0 ClockId0004 SD1_0.PF_XCVR_0.LANE0 clock definition on XCVR_8B10B 31 SD1_0.PF_XCVR_0.LANE0 =============================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 135MB) Writing Analyst data base D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\synthesis\synwork\EPCS_TX_RX_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 136MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 136MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) @N:MT615 : | Found clock REF_CLK_PAD_P_0 with period 6.40ns @W:MT420 : | Found inferred clock SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SD1_0.PF_XCVR_REF_CLK_0.FAB_REF_CLK" @W:MT420 : | Found inferred clock SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|REF_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SD1_0.PF_XCVR_REF_CLK_0.REF_CLK" @N:MT615 : | Found clock SD1_0/PF_XCVR_0/LANE0/TX_CLK_G with period 16.00ns @N:MT615 : | Found clock SD1_0/PF_XCVR_0/LANE0/RX_CLK_G with period 16.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Feb 14 11:25:17 2017 # Top view: EPCS_TX_RX Requested Frequency: 62.5 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\Appsnotes\2016\PF_Multi_rate_XVR_demo\Designs\Posted_design\PF_SERDES_8b10b\designer\EPCS_TX_RX\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 9.136 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- REF_CLK_PAD_P_0 156.3 MHz NA 6.400 NA NA declared default_clkgroup SD1_0/PF_XCVR_0/LANE0/RX_CLK_G 62.5 MHz 173.1 MHz 16.000 5.778 10.222 declared default_clkgroup SD1_0/PF_XCVR_0/LANE0/TX_CLK_G 62.5 MHz 173.1 MHz 16.000 5.778 13.210 declared default_clkgroup SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock 100.0 MHz 1157.8 MHz 10.000 0.864 9.136 inferred Inferred_clkgroup_1 SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|REF_CLK_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 ========================================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SD1_0/PF_XCVR_0/LANE0/TX_CLK_G | 16.000 13.210 | No paths - | No paths - | No paths - SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SD1_0/PF_XCVR_0/LANE0/TX_CLK_G | 16.000 10.222 | No paths - | No paths - | No paths - SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SD1_0/PF_XCVR_0/LANE0/RX_CLK_G | 16.000 11.532 | No paths - | No paths - | No paths - SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SD1_0/PF_XCVR_0/LANE0/RX_CLK_G | Diff grp - | No paths - | No paths - | No paths - SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock | 10.000 9.136 | No paths - | No paths - | No paths - =========================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: SD1_0/PF_XCVR_0/LANE0/RX_CLK_G ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------ SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[1] SD1_0_LANE0_RX_DATA[1] 2.950 10.222 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[2] SD1_0_LANE0_RX_DATA[2] 2.941 10.273 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[3] SD1_0_LANE0_RX_DATA[3] 2.978 10.317 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[13] SD1_0_LANE0_RX_DATA[13] 2.868 10.346 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[4] SD1_0_LANE0_RX_DATA[4] 2.860 10.385 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[0] SD1_0_LANE0_RX_DATA[0] 2.968 10.424 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[5] SD1_0_LANE0_RX_DATA[5] 2.855 10.440 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[7] SD1_0_LANE0_RX_DATA[7] 2.879 10.448 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[12] SD1_0_LANE0_RX_DATA[12] 2.878 10.515 SD1_0.PF_XCVR_0.LANE0 SD1_0/PF_XCVR_0/LANE0/RX_CLK_G XCVR_8B10B RX_DATA[15] SD1_0_LANE0_RX_DATA[15] 2.834 10.528 ========================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- count_gen_0.sm[3] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE D sm_ns[3] 16.000 10.222 count_gen_0.k_out[0] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN un1_sm_7_i 15.909 10.377 count_gen_0.k_out[1] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN un1_sm_7_i 15.909 10.377 count_gen_0.rxslip SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE D N_16_i 16.000 10.582 count_gen_0.sm[2] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE D N_36_i 16.000 10.582 count_gen_0.rxslip SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN N_14_i 15.909 10.637 count_check_0.reg_error_out SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN un1_reg_error13_i 15.909 11.532 count_gen_0.data_out_1[0] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN un1_sm_3_i 15.909 11.566 count_gen_0.data_out_1[1] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN un1_sm_3_i 15.909 11.566 count_gen_0.data_out_1[2] SD1_0/PF_XCVR_0/LANE0/RX_CLK_G SLE EN un1_sm_3_i 15.909 11.566 ============================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 16.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 16.000 - Propagation time: 5.778 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 10.222 Number of logic level(s): 4 Starting point: SD1_0.PF_XCVR_0.LANE0 / RX_DATA[1] Ending point: count_gen_0.sm[3] / D The start point is clocked by SD1_0/PF_XCVR_0/LANE0/RX_CLK_G [rising] on pin RX_FWF_CLK The end point is clocked by SD1_0/PF_XCVR_0/LANE0/TX_CLK_G [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------ SD1_0.PF_XCVR_0.LANE0 XCVR_8B10B RX_DATA[1] Out 2.950 2.950 - SD1_0_LANE0_RX_DATA[1] Net - - 0.974 - 2 count_gen_0.un1_sm_7_0_a2_0_11 CFG4 D In - 3.924 - count_gen_0.un1_sm_7_0_a2_0_11 CFG4 Y Out 0.293 4.217 - un1_sm_7_0_a2_0_11 Net - - 0.167 - 1 count_gen_0.un1_sm_7_0_a2_0 CFG4 D In - 4.384 - count_gen_0.un1_sm_7_0_a2_0 CFG4 Y Out 0.282 4.666 - N_112 Net - - 0.380 - 5 count_gen_0.sm_ns_4_0_.m50_0_a2_2 CFG4 C In - 5.046 - count_gen_0.sm_ns_4_0_.m50_0_a2_2 CFG4 Y Out 0.251 5.297 - N_99 Net - - 0.167 - 1 count_gen_0.sm_ns_4_0_.m50_0 CFG4 C In - 5.463 - count_gen_0.sm_ns_4_0_.m50_0 CFG4 Y Out 0.251 5.714 - sm_ns[3] Net - - 0.064 - 1 count_gen_0.sm[3] SLE D In - 5.778 - ============================================================================================================ Total path delay (propagation time + setup) of 5.778 is 4.027(69.7%) logic and 1.751(30.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SD1_0/PF_XCVR_0/LANE0/TX_CLK_G ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- count_gen_0.sm[3] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q sm_0[3] 0.122 13.210 count_gen_0.c[3] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[3] 0.122 13.258 count_gen_0.sm[4] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q sm_0[4] 0.122 13.262 count_gen_0.c[1] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[1] 0.122 13.325 count_gen_0.c[0] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[0] 0.122 13.369 count_gen_0.c[2] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[2] 0.122 13.395 count_gen_0.c[4] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[4] 0.122 13.455 count_gen_0.c[5] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[5] 0.122 13.468 count_gen_0.c[6] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q c[6] 0.122 13.481 count_gen_0.data_out_1[7] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE Q count_gen_0_data_out[7] 0.171 13.687 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------- count_gen_0.c[7] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_6[7] 16.000 13.210 count_gen_0.c[0] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_6[0] 16.000 13.258 count_gen_0.c[1] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_6[1] 16.000 13.258 count_gen_0.c[2] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_6[2] 16.000 13.258 count_gen_0.sm[3] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D sm_ns[3] 16.000 13.258 count_gen_0.c[6] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_RNIGRQG1_S[6] 16.000 13.456 count_gen_0.c[5] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_RNI03MA1_S[5] 16.000 13.469 count_gen_0.c[4] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_RNIHBH41_S[4] 16.000 13.482 count_gen_0.c[3] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D c_RNI3LCU_S[3] 16.000 13.495 count_gen_0.sm[4] SD1_0/PF_XCVR_0/LANE0/TX_CLK_G SLE D N_38 16.000 13.681 ================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 16.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 16.000 - Propagation time: 2.791 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 13.210 Number of logic level(s): 10 Starting point: count_gen_0.sm[3] / Q Ending point: count_gen_0.c[7] / D The start point is clocked by SD1_0/PF_XCVR_0/LANE0/TX_CLK_G [rising] on pin CLK The end point is clocked by SD1_0/PF_XCVR_0/LANE0/TX_CLK_G [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------- count_gen_0.sm[3] SLE Q Out 0.122 0.122 - sm_0[3] Net - - 0.646 - 14 count_gen_0.sm_RNIL5Q5[4] ARI1 B In - 0.768 - count_gen_0.sm_RNIL5Q5[4] ARI1 FCO Out 0.428 1.196 - un1_c_1_cry_0_cy Net - - 0.000 - 1 count_gen_0.c_RNIVNUB[0] ARI1 FCI In - 1.196 - count_gen_0.c_RNIVNUB[0] ARI1 FCO Out 0.013 1.209 - un1_c_1_cry_0 Net - - 0.000 - 1 count_gen_0.c_RNIAB3I[1] ARI1 FCI In - 1.209 - count_gen_0.c_RNIAB3I[1] ARI1 FCO Out 0.013 1.222 - un1_c_1_cry_1 Net - - 0.000 - 1 count_gen_0.c_RNIMV7O[2] ARI1 FCI In - 1.222 - count_gen_0.c_RNIMV7O[2] ARI1 FCO Out 0.013 1.235 - un1_c_1_cry_2 Net - - 0.000 - 1 count_gen_0.c_RNI3LCU[3] ARI1 FCI In - 1.235 - count_gen_0.c_RNI3LCU[3] ARI1 FCO Out 0.013 1.248 - un1_c_1_cry_3 Net - - 0.000 - 1 count_gen_0.c_RNIHBH41[4] ARI1 FCI In - 1.248 - count_gen_0.c_RNIHBH41[4] ARI1 FCO Out 0.013 1.261 - un1_c_1_cry_4 Net - - 0.000 - 1 count_gen_0.c_RNI03MA1[5] ARI1 FCI In - 1.261 - count_gen_0.c_RNI03MA1[5] ARI1 FCO Out 0.013 1.274 - un1_c_1_cry_5 Net - - 0.000 - 1 count_gen_0.c_RNIGRQG1[6] ARI1 FCI In - 1.274 - count_gen_0.c_RNIGRQG1[6] ARI1 FCO Out 0.013 1.287 - un1_c_1_cry_6 Net - - 0.000 - 1 count_gen_0.c_6_RNO[7] ARI1 FCI In - 1.287 - count_gen_0.c_6_RNO[7] ARI1 S Out 0.322 1.609 - c_6_RNO_S[7] Net - - 0.948 - 1 count_gen_0.c_6[7] CFG2 B In - 2.557 - count_gen_0.c_6[7] CFG2 Y Out 0.170 2.726 - c_6[7] Net - - 0.064 - 1 count_gen_0.c[7] SLE D In - 2.791 - ======================================================================================== Total path delay (propagation time + setup) of 2.791 is 1.132(40.6%) logic and 1.659(59.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- count_check_0.tx_req_d2 SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE Q tx_req_d2 0.122 9.136 count_check_0.tx_req_d1 SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE Q tx_req_d1 0.171 9.549 ================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------- count_check_0.error_count[0] SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.error_count[1] SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.error_count[2] SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.error_count[3] SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.error_count[4] SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.error_count[5] SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.error_out SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.lock SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE EN tx_req_d2 9.909 9.136 count_check_0.rx_ack SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE D tx_req_d2 10.000 9.178 count_check_0.tx_req_d2 SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock SLE D tx_req_d1 10.000 9.549 ======================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.091 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.909 - Propagation time: 0.772 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 9.136 Number of logic level(s): 0 Starting point: count_check_0.tx_req_d2 / Q Ending point: count_check_0.error_count[0] / EN The start point is clocked by SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock [rising] on pin CLK The end point is clocked by SD1_PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK|FAB_REF_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- count_check_0.tx_req_d2 SLE Q Out 0.122 0.122 - tx_req_d2 Net - - 0.650 - 9 count_check_0.error_count[0] SLE EN In - 0.772 - =========================================================================================== Total path delay (propagation time + setup) of 0.864 is 0.213(24.7%) logic and 0.650(75.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) --------------------------------------- Resource Usage Report for EPCS_TX_RX Mapping to part: pa5m300fbga896std Cell usage: CLKINT 3 uses TX_PLL 1 use XCVR_8B10B 1 use XCVR_REF_CLK 1 use CFG1 3 uses CFG2 13 uses CFG3 16 uses CFG4 25 uses Carry cells: ARI1 33 uses - used for arithmetic functions Sequential Cells: SLE 92 uses DSP Blocks: 0 of 924 (0%) I/O ports: 18 I/O primitives: 12 INBUF 3 uses OUTBUF 9 uses Global Clock Buffers: 3 of 8 (37%) Total LUTs: 90 Extra resources required for RAM and MACC_PA interface logic during P&R: RAM64X12 Interface Logic : SLEs = 0; LUTs = 0; RAM1K20 Interface Logic : SLEs = 0; LUTs = 0; MACC_PA Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 92 + 0 + 0 + 0 = 92; Total number of LUTs after P&R: 90 + 0 + 0 + 0 = 90; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 28MB peak: 136MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 14 11:25:17 2017 ###########################################################]