#Build: Synplify Pro J-2015.03M-3, Build 048R, May 14 2015 #install: C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3 #OS: Windows 7 6.1 #Hostname: I5 #Implementation: synthesis Synopsys HDL Compiler, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\hypermods.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\lib\vlog\scemi_pipes.svh" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb\CCC_0\m2s060_som_sb_CCC_0_FCCC.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\SgCore\OSC\1.0.105\osc_comps.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb\FABOSC_0\m2s060_som_sb_FABOSC_0_OSC.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb_MSS\m2s060_som_sb_MSS_syn.v" @W:CG289 : m2s060_som_sb_MSS_syn.v(1946) | Specified digits overflow the number's size @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb_MSS\m2s060_som_sb_MSS.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb\m2s060_som_sb.v" @I::"C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som\m2s060_som.v" Verilog syntax check successful! File C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb\CCC_0\m2s060_som_sb_CCC_0_FCCC.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\Actel\SgCore\OSC\1.0.105\osc_comps.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb\FABOSC_0\m2s060_som_sb_FABOSC_0_OSC.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb_MSS\m2s060_som_sb_MSS_syn.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb_MSS\m2s060_som_sb_MSS.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som_sb\m2s060_som_sb.v changed - recompiling File C:\Actelprj\m2s060-som-fg484-1a-116\component\work\m2s060_som\m2s060_som.v changed - recompiling Selecting top level module m2s060_som @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : m2s060_som_sb_CCC_0_FCCC.v(5) | Synthesizing module m2s060_som_sb_CCC_0_FCCC @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z1 @W:CL113 : coreconfigp.v(626) | Feedback mux created for signal soft_reset_reg[16:0]. @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @W:CL250 : coreconfigp.v(626) | All reachable assignments to soft_reset_reg[16:0] assign 0, register removed by optimization @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000011 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z2 @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : osc_comps.v(23) | Synthesizing module XTLOSC @N:CG364 : m2s060_som_sb_FABOSC_0_OSC.v(5) | Synthesizing module m2s060_som_sb_FABOSC_0_OSC @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : m2s060_som_sb_MSS_syn.v(5) | Synthesizing module MSS_060 @N:CG364 : m2s060_som_sb_MSS.v(9) | Synthesizing module m2s060_som_sb_MSS @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : m2s060_som_sb.v(9) | Synthesizing module m2s060_som_sb @N:CG364 : m2s060_som.v(9) | Synthesizing module m2s060_som @W:CL157 : m2s060_som_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : m2s060_som_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : m2s060_som_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : m2s060_som_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1433) | Trying to extract state machine for register sm2_state Extracted state machine for register sm2_state State machine has 2 reachable states with original encodings of: 000 001 @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused @W:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 08 18:12:19 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 08 18:12:19 2015 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 08 18:12:19 2015 ###########################################################] Synopsys Netlist Linker, version comp201503p1, Build 094R, built May 14 2015 @N: : | Running in 64-bit mode File C:\Actelprj\m2s060-som-fg484-1a-116\synthesis\synwork\m2s060_som_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 08 18:12:21 2015 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: m2s060_som_scck.rpt Printing clock summary report in "C:\Actelprj\m2s060-som-fg484-1a-116\synthesis\m2s060_som_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 109MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.release_ext_reset, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.SDIF_READY_int @W:BN132 : coreresetp.v(1089) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1433) | Removing sequential instance EXT_RESET_OUT_int of view:PrimLib.dffse(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1433) | Removing sequential instance sm2_state[1:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(783) | Removing sequential instance sm2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(783) | Removing sequential instance sm2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=69 set on top level netlist m2s060_som Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------------------------------------------------------- System 100.0 MHz 10.000 system system_clkgroup m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_4 m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 m2s060_som|MAC_MII_RX_CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_3 m2s060_som|MAC_MII_TX_CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_2 ================================================================================================================================== @W:MT530 : coreconfigp.v(546) | Found inferred clock m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 93 sequential elements including m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1089) | Found inferred clock m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 55 sequential elements including m2s060_som_sb_0.CORERESETP_0.count_ddr_enable. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : m2s060_som_sb_mss.v(1431) | Found inferred clock m2s060_som|MAC_MII_TX_CLK which controls 0 sequential elements including m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : m2s060_som_sb_mss.v(1431) | Found inferred clock m2s060_som|MAC_MII_RX_CLK which controls 0 sequential elements including m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1613) | Found inferred clock m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 31 sequential elements including m2s060_som_sb_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Actelprj\m2s060-som-fg484-1a-116\synthesis\m2s060_som.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 137MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 08 18:12:21 2015 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version map201503actrcp1, Build 002R, Built Jul 1 2015 06:58:23 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-3 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) @W:MO111 : m2s060_som_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module m2s060_som_sb_FABOSC_0_OSC) @W:MO111 : m2s060_som_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module m2s060_som_sb_FABOSC_0_OSC) @W:MO111 : m2s060_som_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module m2s060_som_sb_FABOSC_0_OSC) @W:MO111 : m2s060_som_sb_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module m2s060_som_sb_FABOSC_0_OSC) @W:MO171 : coreresetp.v(676) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance m2s060_som_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance m2s060_som_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance m2s060_som_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance m2s060_som_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : coreconfigp.v(583) | Sequential instance m2s060_som_sb_0.CORECONFIGP_0.SDIF_RELEASED_q1 reduced to a combinational gate by constant propagation @W:BN132 : coreresetp.v(884) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(912) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(856) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif2_areset_n_rcosc, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(912) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif3_areset_n_rcosc, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(884) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif1_areset_n_rcosc, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(870) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.sdif0_areset_n_rcosc, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(1581) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.release_sdif3_core, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.release_sdif2_core @W:BN132 : coreresetp.v(1549) | Removing sequential instance m2s060_som_sb_0.CORERESETP_0.release_sdif2_core, because it is equivalent to instance m2s060_som_sb_0.CORERESETP_0.release_sdif1_core Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Encoding state machine CORECONFIGP_0.state[2:0] (view:work.m2s060_som_sb(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[31] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[30] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[29] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[28] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[27] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[26] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[25] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[24] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[23] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[22] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[21] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[20] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[19] is always 0, optimizing ... @W:MO160 : coreconfigp.v(255) | Register bit CORECONFIGP_0.paddr[16] is always 0, optimizing ... @N:BN362 : coreconfigp.v(255) | Removing sequential instance CORECONFIGP_0.paddr[14] of view:PrimLib.dffr(prim) in hierarchy view:work.m2s060_som_sb(verilog) because there are no references to its outputs Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z2(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z2(verilog) inst count_ddr[13:0] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 1.28ns 118 / 106 2 0h:00m:00s 1.28ns 118 / 106 @N:FP130 : | Promoting Net m2s060_som_sb_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT I_28 @N:FP130 : | Promoting Net m2s060_som_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT I_29 @N:FP130 : | Promoting Net m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_30 @N:FP130 : | Promoting Net m2s060_som_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_31 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 135MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 4 non-gated/non-generated clock tree(s) driving 53 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 57 clock pin(s) of sequential element(s) 0 instances converted, 57 sequential instances remain driven by gated/generated clocks =============================================================== Non-Gated/Non-Generated Clocks ================================================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 MAC_MII_TX_CLK port 1 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST ClockId0003 MAC_MII_RX_CLK port 1 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST ClockId0004 m2s060_som_sb_0.CCC_0.GL0_INST CLKINT 31 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST ClockId0005 m2s060_som_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 20 m2s060_som_sb_0.CORERESETP_0.count_ddr[13] =============================================================================================================================================================== ================================================================================================== Gated/Generated Clocks =================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST MSS_060 57 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_060 ============================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 135MB) Writing Analyst data base C:\Actelprj\m2s060-som-fg484-1a-116\synthesis\synwork\m2s060_som_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-3 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) @W:MT246 : m2s060_som_sb_fabosc_0_osc.v(28) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : m2s060_som_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock m2s060_som|MAC_MII_RX_CLK with period 10.00ns. Please declare a user-defined clock on object "p:MAC_MII_RX_CLK" @W:MT420 : | Found inferred clock m2s060_som|MAC_MII_TX_CLK with period 10.00ns. Please declare a user-defined clock on object "p:MAC_MII_TX_CLK" @W:MT420 : | Found inferred clock m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:m2s060_som_sb_0.m2s060_som_sb_MSS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:m2s060_som_sb_0.FABOSC_0.N_RCOSC_25_50MHZ_CLKOUT" @W:MT420 : | Found inferred clock m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:m2s060_som_sb_0.CCC_0.GL0_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Sun Nov 08 18:12:23 2015 # Top view: m2s060_som Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.286 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 407.0 MHz 10.000 2.457 7.543 inferred Inferred_clkgroup_1 m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 355.3 MHz 10.000 2.814 7.186 inferred Inferred_clkgroup_4 m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 130.0 MHz 10.000 7.693 1.286 inferred Inferred_clkgroup_0 m2s060_som|MAC_MII_RX_CLK 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_3 m2s060_som|MAC_MII_TX_CLK 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_2 System 100.0 MHz 895.2 MHz 10.000 1.117 8.883 system system_clkgroup ======================================================================================================================================================================== @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 8.883 | No paths - | No paths - | No paths - m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 2.307 | No paths - | 5.000 2.532 | 5.000 1.286 m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 7.543 | No paths - | No paths - | No paths - m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 10.000 7.186 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORERESETP_0.sm0_state[3] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[3] 0.087 7.543 m2s060_som_sb_0.CORERESETP_0.sdif3_spll_lock_q2 m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sdif3_spll_lock_q2 0.087 7.630 m2s060_som_sb_0.CORERESETP_0.release_sdif0_core_clk_base m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q release_sdif3_core_clk_base 0.087 7.940 m2s060_som_sb_0.CORERESETP_0.ddr_settled_clk_base m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q ddr_settled_clk_base 0.087 7.968 m2s060_som_sb_0.CORERESETP_0.sm0_state[4] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[4] 0.108 8.193 m2s060_som_sb_0.CORERESETP_0.CONFIG2_DONE_clk_base m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q CONFIG2_DONE_clk_base 0.108 8.361 m2s060_som_sb_0.CORERESETP_0.sm0_state[5] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q sm0_state[5] 0.108 8.557 m2s060_som_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q FIC_2_APB_M_PRESET_N_clk_base 0.087 8.615 m2s060_som_sb_0.CORERESETP_0.RESET_N_M2F_clk_base m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q RESET_N_M2F_clk_base 0.087 8.632 m2s060_som_sb_0.CORERESETP_0.mss_ready_state m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q mss_ready_state 0.108 8.646 ======================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ m2s060_som_sb_0.CORERESETP_0.sm0_state[4] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[4] 9.745 7.543 m2s060_som_sb_0.CORERESETP_0.sm0_state[5] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[5] 9.745 7.940 m2s060_som_sb_0.CORERESETP_0.count_ddr_enable m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D next_count_ddr_enable_0_sqmuxa 9.745 8.130 m2s060_som_sb_0.CORERESETP_0.count_ddr_enable m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN un1_next_ddr_ready_0_sqmuxa 9.662 8.193 m2s060_som_sb_0.CORERESETP_0.sm0_state[3] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[3] 9.745 8.303 m2s060_som_sb_0.CORERESETP_0.sm0_state[6] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN sm0_state_ns_a3[6] 9.662 8.557 m2s060_som_sb_0.CORERESETP_0.MSS_HPMS_READY_int m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D MSS_HPMS_READY_int_4 9.745 8.615 m2s060_som_sb_0.CORERESETP_0.mss_ready_select m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN mss_ready_select4 9.662 8.634 m2s060_som_sb_0.CORERESETP_0.sm0_state[2] m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE D sm0_state_ns[2] 9.745 8.650 m2s060_som_sb_0.CORERESETP_0.mss_ready_state m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE EN RESET_N_M2F_clk_base 9.662 8.765 ============================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 2.202 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.543 Number of logic level(s): 2 Starting point: m2s060_som_sb_0.CORERESETP_0.sm0_state[3] / Q Ending point: m2s060_som_sb_0.CORERESETP_0.sm0_state[4] / D The start point is clocked by m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK The end point is clocked by m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORERESETP_0.sm0_state[3] SLE Q Out 0.087 0.087 - sm0_state[3] Net - - 0.733 - 3 m2s060_som_sb_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3 CFG2 B In - 0.821 - m2s060_som_sb_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3 CFG2 Y Out 0.165 0.985 - next_count_ddr_enable_0_sqmuxa Net - - 0.630 - 2 m2s060_som_sb_0.CORERESETP_0.sm0_state_ns[4] CFG4 D In - 1.615 - m2s060_som_sb_0.CORERESETP_0.sm0_state_ns[4] CFG4 Y Out 0.428 2.043 - sm0_state_ns[4] Net - - 0.159 - 1 m2s060_som_sb_0.CORERESETP_0.sm0_state[4] SLE D In - 2.202 - =============================================================================================================================== Total path delay (propagation time + setup) of 2.457 is 0.935(38.1%) logic and 1.522(61.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORERESETP_0.count_ddr[0] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[0] 0.087 7.186 m2s060_som_sb_0.CORERESETP_0.count_ddr[1] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[1] 0.108 7.392 m2s060_som_sb_0.CORERESETP_0.count_ddr[2] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[2] 0.108 7.408 m2s060_som_sb_0.CORERESETP_0.count_ddr[3] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[3] 0.108 7.425 m2s060_som_sb_0.CORERESETP_0.count_ddr[4] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[4] 0.108 7.441 m2s060_som_sb_0.CORERESETP_0.count_ddr[5] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[5] 0.108 7.457 m2s060_som_sb_0.CORERESETP_0.count_ddr[6] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[6] 0.108 7.473 m2s060_som_sb_0.CORERESETP_0.count_ddr[7] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[7] 0.108 7.490 m2s060_som_sb_0.CORERESETP_0.count_ddr[8] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[8] 0.108 7.506 m2s060_som_sb_0.CORERESETP_0.count_ddr[9] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[9] 0.108 7.522 ======================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORERESETP_0.ddr_settled m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE EN ddr_settled4 9.662 7.186 m2s060_som_sb_0.CORERESETP_0.count_ddr[13] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[13] 9.745 7.317 m2s060_som_sb_0.CORERESETP_0.count_ddr[12] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[12] 9.745 7.333 m2s060_som_sb_0.CORERESETP_0.count_ddr[11] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[11] 9.745 7.350 m2s060_som_sb_0.CORERESETP_0.count_ddr[10] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[10] 9.745 7.366 m2s060_som_sb_0.CORERESETP_0.count_ddr[9] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[9] 9.745 7.382 m2s060_som_sb_0.CORERESETP_0.count_ddr[8] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[8] 9.745 7.399 m2s060_som_sb_0.CORERESETP_0.count_ddr[7] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[7] 9.745 7.415 m2s060_som_sb_0.CORERESETP_0.count_ddr[6] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[6] 9.745 7.431 m2s060_som_sb_0.CORERESETP_0.count_ddr[5] m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[5] 9.745 7.447 ============================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.338 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.662 - Propagation time: 2.477 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.186 Number of logic level(s): 2 Starting point: m2s060_som_sb_0.CORERESETP_0.count_ddr[0] / Q Ending point: m2s060_som_sb_0.CORERESETP_0.ddr_settled / EN The start point is clocked by m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK The end point is clocked by m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.087 0.087 - count_ddr[0] Net - - 0.733 - 3 m2s060_som_sb_0.CORERESETP_0.ddr_settled4_9 CFG4 D In - 0.821 - m2s060_som_sb_0.CORERESETP_0.ddr_settled4_9 CFG4 Y Out 0.472 1.293 - ddr_settled4_9 Net - - 0.556 - 1 m2s060_som_sb_0.CORERESETP_0.ddr_settled4 CFG4 D In - 1.849 - m2s060_som_sb_0.CORERESETP_0.ddr_settled4 CFG4 Y Out 0.470 2.318 - ddr_settled4 Net - - 0.159 - 1 m2s060_som_sb_0.CORERESETP_0.ddr_settled SLE EN In - 2.477 - ========================================================================================================== Total path delay (propagation time + setup) of 2.814 is 1.367(48.6%) logic and 1.447(51.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORECONFIGP_0.psel m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.108 1.286 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[5] CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] 5.734 2.307 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[1] CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] 5.702 2.339 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[7] CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] 5.932 2.460 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[3] CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] 5.897 2.495 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[14] CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] 5.868 2.524 m2s060_som_sb_0.CORECONFIGP_0.state[1] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.087 2.532 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[0] CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] 5.433 2.608 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[15] CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] 5.774 2.618 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PRDATA[12] CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] 5.712 2.680 ================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_060 MDDR_FABRIC_PSEL CORECONFIGP_0_MDDR_APBmslave_PSELx 3.915 1.286 m2s060_som_sb_0.CORECONFIGP_0.state[1] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 4.825 1.568 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PREADY m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_31_i_0 4.662 1.712 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 4.745 1.810 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[1] 4.745 1.810 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[5] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 4.745 1.810 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 4.745 1.855 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 4.745 1.855 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 4.745 1.855 m2s060_som_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6] m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.745 1.855 ======================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.085 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.915 - Propagation time: 2.629 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.286 Number of logic level(s): 1 Starting point: m2s060_som_sb_0.CORECONFIGP_0.psel / Q Ending point: m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST / MDDR_FABRIC_PSEL The start point is clocked by m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CORECONFIGP_0.psel SLE Q Out 0.108 0.108 - psel Net - - 0.908 - 4 m2s060_som_sb_0.CORECONFIGP_0.MDDR_PSEL_0_a2 CFG4 D In - 1.017 - m2s060_som_sb_0.CORECONFIGP_0.MDDR_PSEL_0_a2 CFG4 Y Out 0.470 1.486 - CORECONFIGP_0_MDDR_APBmslave_PSELx Net - - 1.143 - 20 m2s060_som_sb_0.m2s060_som_sb_MSS_0.MSS_ADLIB_INST MSS_060 MDDR_FABRIC_PSEL In - 2.629 - ================================================================================================================================ Total path delay (propagation time + setup) of 3.714 is 1.663(44.8%) logic and 2.051(55.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.FABOSC_0.I_XTLOSC System XTLOSC CLKOUT XTLOSC_CCC_OUT_XTLOSC_CCC 0.000 8.883 ========================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------- m2s060_som_sb_0.CCC_0.CCC_INST System CCC XTLOSC XTLOSC_CCC_OUT_XTLOSC_CCC 10.000 8.883 ===================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 8.883 Number of logic level(s): 0 Starting point: m2s060_som_sb_0.FABOSC_0.I_XTLOSC / CLKOUT Ending point: m2s060_som_sb_0.CCC_0.CCC_INST / XTLOSC The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- m2s060_som_sb_0.FABOSC_0.I_XTLOSC XTLOSC CLKOUT Out 0.000 0.000 - XTLOSC_CCC_OUT_XTLOSC_CCC Net - - 1.117 - 1 m2s060_som_sb_0.CCC_0.CCC_INST CCC XTLOSC In - 1.117 - ==================================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 136MB) --------------------------------------- Resource Usage Report for m2s060_som Mapping to part: m2s060fbga484std Cell usage: CCC 1 use CLKINT 6 uses MSS_060 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use XTLOSC 1 use CFG1 2 uses CFG2 27 uses CFG3 6 uses CFG4 21 uses Carry primitives used for arithmetic functions: ARI1 14 uses Sequential Cells: SLE 106 uses DSP Blocks: 0 I/O ports: 100 I/O primitives: 97 BIBUF 37 uses INBUF 19 uses OUTBUF 35 uses OUTBUF_DIFF 1 use TRIBUFF 5 uses Global Clock Buffers: 6 Total LUTs: 70 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 106 + 0 + 0 + 0 = 106; Total number of LUTs after P&R: 70 + 0 + 0 + 0 = 70; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 136MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Nov 08 18:12:23 2015 ###########################################################]