# Timing Analysis for CoreConfigP # (c) 2015 Microsemi Corp. # v1.02 puts "Analyzing CoreConfigP timing... Please wait..." # Checking if the design is in Post-Place and Route state set post_pr "Tool successfully run" set pr_state [ get_tool_state -name "PLACEROUTE" ] if { $pr_state != $post_pr } then { puts "\n\nError: You must have run 'Place and Route' before running this script.\n\n" } else { # Create a temporary script file if { [ file exists "/tmp" ]} { set tmpdir "/tmp" } catch {set tmpdir $::env(TMP) } catch {set tmpdir $::env(TEMP) } set filename "$tmpdir/st_script.tcl" set i 0 while { [ file exists $filename ] } { set filename "$tmpdir/st_script_$i.tcl" incr i } # Write the SmartTime Tcl script set STF [ open $filename w ] set die [ defvar_get -name "BASE_DIE" ] if { $die == "PA4M500" || $die == "PA4M1000" } then { puts $STF { set use_max_delay 0 } } else { puts $STF { set use_max_delay 1 } } puts $STF { proc read_slack {paths} { set res [ split "$paths" "\n" ] foreach l $res { if { [ string first "Path" "$l" ] == 0 } then { set path_info [ split "$l" "," ] set slack [ lindex $path_info 4 ] return $slack } } } set mss_clock_pin {*/INST_MSS_*_IP:CLK_CONFIG_APB} set mss_psel_penable {*/INST_MSS_*_IP:PER2_FABRIC_PENABLE */INST_MSS_*_IP:PER2_FABRIC_PSEL} set ccp_internal_regs {*/FIC_2_APB_M_PREADY* */state[0]:D} proc get_worst_slack {type opcond} { upvar 1 mss_clock_pin mcp upvar 1 ccp_internal_regs cir set_options -max_opcond $opcond -min_opcond $opcond return [ read_slack [ list_paths -format CSV -analysis $type -from "$mcp" -to "$cir" ] ] } set fic2_clock [ list_objects [ get_pins $mss_clock_pin ] ] # Checking if CoreConfigP can be found in the design. if { $fic2_clock == "" || [ list_objects [ get_pins $mss_psel_penable ] ] == "" || [ list_objects [ get_pins $ccp_internal_regs ] ] == "" } then { puts "\n\nYour design does not contain a CoreConfigP component connected to the MSS FIC_2 interface.\n\n" exit 0 } # Checking if APB_CONFIG_CLK has a clock constraint set fic2_slack [ read_slack [ list_paths -format CSV -analysis max -from $mss_clock_pin -to $ccp_internal_regs ] ] if { $fic2_slack == "" } then { puts "\n\nYou must set a clock constraint on $fic2_clock before running the script.\n\n" exit 0 } # Setting constraints between MSS FIC2 interface and CoreConfigP set_min_delay -24 -from [ get_pins "$mss_clock_pin" ] if { $use_max_delay == 1 } then { set_max_delay 0 -from [ get_pins "$mss_clock_pin" ] \ -through [ get_pins "$mss_psel_penable" ] \ -to [ get_pins "$ccp_internal_regs" ] } else { set_min_delay 0 -from [ get_pins "$mss_clock_pin" ] \ -through [ get_pins "$mss_psel_penable" ] \ -to [ get_pins "$ccp_internal_regs" ] } # Setting false-paths for CoreResetP asynchronous interface set inst "" set cells [ list_objects [ get_cells "*" ] ] foreach cell $cells \ { if { [regexp -nocase {(.*CoreResetP_0)/.*} $cell -> inst] } \ { break } } if { [string length $inst] != 0 } \ { set false_paths \ { {/ddr_settled:CLK /ddr_settled_q1:D} {/release_sdif0_core:CLK /release_sdif0_core_q1:D} {/release_sdif1_core:CLK /release_sdif1_core_q1:D} {/release_sdif2_core:CLK /release_sdif2_core_q1:D} {/release_sdif3_core:CLK /release_sdif3_core_q1:D} {/MSS_HPMS_READY_int:CLK /sm0_areset_n_rcosc_q1:ALn} {/MSS_HPMS_READY_int:CLK /sm0_areset_n_rcosc:ALn} {/MSS_HPMS_READY_int:CLK /sdif0_areset_n_rcosc_q1:ALn} {/MSS_HPMS_READY_int:CLK /sdif0_areset_n_rcosc:ALn} {/MSS_HPMS_READY_int:CLK /sdif1_areset_n_rcosc_q1:ALn} {/MSS_HPMS_READY_int:CLK /sdif1_areset_n_rcosc:ALn} {/MSS_HPMS_READY_int:CLK /sdif2_areset_n_rcosc_q1:ALn} {/MSS_HPMS_READY_int:CLK /sdif2_areset_n_rcosc:ALn} {/MSS_HPMS_READY_int:CLK /sdif3_areset_n_rcosc_q1:ALn} {/MSS_HPMS_READY_int:CLK /sdif3_areset_n_rcosc:ALn} {/SDIF0_PERST_N_re:CLK /sdif0_areset_n_rcosc_q1:ALn} {/SDIF0_PERST_N_re:CLK /sdif0_areset_n_rcosc:ALn} {/SDIF1_PERST_N_re:CLK /sdif1_areset_n_rcosc_q1:ALn} {/SDIF1_PERST_N_re:CLK /sdif1_areset_n_rcosc:ALn} {/SDIF2_PERST_N_re:CLK /sdif2_areset_n_rcosc_q1:ALn} {/SDIF2_PERST_N_re:CLK /sdif2_areset_n_rcosc:ALn} {/SDIF3_PERST_N_re:CLK /sdif3_areset_n_rcosc_q1:ALn} {/SDIF3_PERST_N_re:CLK /sdif3_areset_n_rcosc:ALn} {/count_sdif0_enable:CLK /count_sdif0_enable_q1:D} {/count_sdif1_enable:CLK /count_sdif1_enable_q1:D} {/count_sdif2_enable:CLK /count_sdif2_enable_q1:D} {/count_sdif3_enable:CLK /count_sdif3_enable_q1:D} {/count_ddr_enable:CLK /count_ddr_enable_q1:D} {/SDIF0_CORE_RESET_N_0:CLK /genblk2.sdif0_phr/reset_n_q1:ALn} {/SDIF0_CORE_RESET_N_0:CLK /genblk2.sdif0_phr/reset_n_clk_ltssm:ALn} {/SDIF1_CORE_RESET_N_0:CLK /genblk3.sdif1_phr/reset_n_q1:ALn} {/SDIF1_CORE_RESET_N_0:CLK /genblk3.sdif1_phr/reset_n_clk_ltssm:ALn} {/SDIF2_CORE_RESET_N_0:CLK /genblk4.sdif2_phr/reset_n_q1:ALn} {/SDIF2_CORE_RESET_N_0:CLK /genblk4.sdif2_phr/reset_n_clk_ltssm:ALn} {/SDIF3_CORE_RESET_N_0:CLK /genblk5.sdif3_phr/reset_n_q1:ALn} {/SDIF3_CORE_RESET_N_0:CLK /genblk5.sdif3_phr/reset_n_clk_ltssm:ALn} {/genblk2.sdif0_phr/hot_reset_n:CLK /genblk2.sdif0_phr/sdif_core_reset_n_q1:ALn} {/genblk2.sdif0_phr/hot_reset_n:CLK /genblk2.sdif0_phr/sdif_core_reset_n:ALn} {/genblk3.sdif1_phr/hot_reset_n:CLK /genblk3.sdif1_phr/sdif_core_reset_n_q1:ALn} {/genblk3.sdif1_phr/hot_reset_n:CLK /genblk3.sdif1_phr/sdif_core_reset_n:ALn} {/genblk4.sdif2_phr/hot_reset_n:CLK /genblk4.sdif2_phr/sdif_core_reset_n_q1:ALn} {/genblk4.sdif2_phr/hot_reset_n:CLK /genblk4.sdif2_phr/sdif_core_reset_n:ALn} {/genblk5.sdif3_phr/hot_reset_n:CLK /genblk5.sdif3_phr/sdif_core_reset_n_q1:ALn} {/genblk5.sdif3_phr/hot_reset_n:CLK /genblk5.sdif3_phr/sdif_core_reset_n:ALn} {* /genblk2.sdif0_phr/ltssm_q1[0]:D} {* /genblk2.sdif0_phr/ltssm_q1[1]:D} {* /genblk2.sdif0_phr/ltssm_q1[2]:D} {* /genblk2.sdif0_phr/ltssm_q1[3]:D} {* /genblk2.sdif0_phr/ltssm_q1[4]:D} {* /genblk2.sdif0_phr/psel_q1:D} {* /genblk2.sdif0_phr/pwrite_q1:D} {* /genblk3.sdif1_phr/ltssm_q1[0]:D} {* /genblk3.sdif1_phr/ltssm_q1[1]:D} {* /genblk3.sdif1_phr/ltssm_q1[2]:D} {* /genblk3.sdif1_phr/ltssm_q1[3]:D} {* /genblk3.sdif1_phr/ltssm_q1[4]:D} {* /genblk3.sdif1_phr/psel_q1:D} {* /genblk3.sdif1_phr/pwrite_q1:D} {* /genblk4.sdif2_phr/ltssm_q1[0]:D} {* /genblk4.sdif2_phr/ltssm_q1[1]:D} {* /genblk4.sdif2_phr/ltssm_q1[2]:D} {* /genblk4.sdif2_phr/ltssm_q1[3]:D} {* /genblk4.sdif2_phr/ltssm_q1[4]:D} {* /genblk4.sdif2_phr/psel_q1:D} {* /genblk4.sdif2_phr/pwrite_q1:D} {* /genblk5.sdif3_phr/ltssm_q1[0]:D} {* /genblk5.sdif3_phr/ltssm_q1[1]:D} {* /genblk5.sdif3_phr/ltssm_q1[2]:D} {* /genblk5.sdif3_phr/ltssm_q1[3]:D} {* /genblk5.sdif3_phr/ltssm_q1[4]:D} {* /genblk5.sdif3_phr/psel_q1:D} {* /genblk5.sdif3_phr/pwrite_q1:D} {/SDIF0_CORE_RESET_N_0:CLK /SDIF0_HR_FIX_INCLUDED.sdif0_phr/reset_n_q1:ALn} {/SDIF0_CORE_RESET_N_0:CLK /SDIF0_HR_FIX_INCLUDED.sdif0_phr/reset_n_clk_ltssm:ALn} {/SDIF1_CORE_RESET_N_0:CLK /SDIF1_HR_FIX_INCLUDED.sdif1_phr/reset_n_q1:ALn} {/SDIF1_CORE_RESET_N_0:CLK /SDIF1_HR_FIX_INCLUDED.sdif1_phr/reset_n_clk_ltssm:ALn} {/SDIF2_CORE_RESET_N_0:CLK /SDIF2_HR_FIX_INCLUDED.sdif2_phr/reset_n_q1:ALn} {/SDIF2_CORE_RESET_N_0:CLK /SDIF2_HR_FIX_INCLUDED.sdif2_phr/reset_n_clk_ltssm:ALn} {/SDIF3_CORE_RESET_N_0:CLK /SDIF3_HR_FIX_INCLUDED.sdif3_phr/reset_n_q1:ALn} {/SDIF3_CORE_RESET_N_0:CLK /SDIF3_HR_FIX_INCLUDED.sdif3_phr/reset_n_clk_ltssm:ALn} {/SDIF0_HR_FIX_INCLUDED.sdif0_phr/hot_reset_n:CLK /SDIF0_HR_FIX_INCLUDED.sdif0_phr/sdif_core_reset_n_q1:ALn} {/SDIF0_HR_FIX_INCLUDED.sdif0_phr/hot_reset_n:CLK /SDIF0_HR_FIX_INCLUDED.sdif0_phr/sdif_core_reset_n:ALn} {/SDIF1_HR_FIX_INCLUDED.sdif1_phr/hot_reset_n:CLK /SDIF1_HR_FIX_INCLUDED.sdif1_phr/sdif_core_reset_n_q1:ALn} {/SDIF1_HR_FIX_INCLUDED.sdif1_phr/hot_reset_n:CLK /SDIF1_HR_FIX_INCLUDED.sdif1_phr/sdif_core_reset_n:ALn} {/SDIF2_HR_FIX_INCLUDED.sdif2_phr/hot_reset_n:CLK /SDIF2_HR_FIX_INCLUDED.sdif2_phr/sdif_core_reset_n_q1:ALn} {/SDIF2_HR_FIX_INCLUDED.sdif2_phr/hot_reset_n:CLK /SDIF2_HR_FIX_INCLUDED.sdif2_phr/sdif_core_reset_n:ALn} {/SDIF3_HR_FIX_INCLUDED.sdif3_phr/hot_reset_n:CLK /SDIF3_HR_FIX_INCLUDED.sdif3_phr/sdif_core_reset_n_q1:ALn} {/SDIF3_HR_FIX_INCLUDED.sdif3_phr/hot_reset_n:CLK /SDIF3_HR_FIX_INCLUDED.sdif3_phr/sdif_core_reset_n:ALn} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/ltssm_q1[0]:D} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/ltssm_q1[1]:D} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/ltssm_q1[2]:D} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/ltssm_q1[3]:D} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/ltssm_q1[4]:D} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/psel_q1:D} {* /SDIF0_HR_FIX_INCLUDED.sdif0_phr/pwrite_q1:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/ltssm_q1[0]:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/ltssm_q1[1]:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/ltssm_q1[2]:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/ltssm_q1[3]:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/ltssm_q1[4]:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/psel_q1:D} {* /SDIF1_HR_FIX_INCLUDED.sdif1_phr/pwrite_q1:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/ltssm_q1[0]:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/ltssm_q1[1]:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/ltssm_q1[2]:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/ltssm_q1[3]:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/ltssm_q1[4]:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/psel_q1:D} {* /SDIF2_HR_FIX_INCLUDED.sdif2_phr/pwrite_q1:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/ltssm_q1[0]:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/ltssm_q1[1]:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/ltssm_q1[2]:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/ltssm_q1[3]:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/ltssm_q1[4]:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/psel_q1:D} {* /SDIF3_HR_FIX_INCLUDED.sdif3_phr/pwrite_q1:D} } foreach false_path $false_paths { set from_pin [lindex $false_path 0] set to_pin [lindex $false_path 1] if { ${from_pin} == "*" } then { set pins [ list_objects [ get_pins "$inst${to_pin}" ] ] if { [ llength $pins ] == 1 } then { set_false_path -to [ get_pins ${pins} ] } } else { set from_pins [ list_objects [ get_pins "$inst${from_pin}" ] ] set to_pins [ list_objects [ get_pins "$inst${to_pin}" ] ] if { ([llength $from_pins] == 1) && ([llength $to_pins] == 1)} then { set_false_path -from [ get_pins ${from_pins} ] -to [ get_pins ${to_pins} ] } } } } # Saving constraints save # Check timing between MSS FIC_2 and CoreConfigP if { $use_max_delay == 1 } then { set_min_delay 0 -from [ get_pins "$mss_clock_pin" ] \ -through [ get_pins "$mss_psel_penable" ] \ -to [ get_pins "$ccp_internal_regs" ] } else { set_max_delay 0 -from [ get_pins "$mss_clock_pin" ] \ -through [ get_pins "$mss_psel_penable" ] \ -to [ get_pins "$ccp_internal_regs" ] } set wc_max_slack [ get_worst_slack "max" "worst" ] set bc_max_slack [ get_worst_slack "max" "best" ] set wc_min_slack [ get_worst_slack "min" "worst" ] set bc_min_slack [ get_worst_slack "min" "best" ] set success "\n\nYour design does not have any 'true' hold violations in the CLK_CONFIG_APB clock domain between the MSS FIC_2 interface and the CoreConfigP component.\n\n" set failure "\n\nYour design has hold violations in the CLK_CONFIG_APB clock domain between the MSS FIC_2 interface and the CoreConfigP component connected to it. Please contact Microsemi Tech Support.\n\n" if { $wc_max_slack >= 0 } then { if { $bc_max_slack < 0 || $wc_min_slack >= 0 || $bc_min_slack >= 0 } then { puts $failure } else { puts $success } } else { if { $bc_max_slack >= 0 || $wc_min_slack < 0 || $bc_min_slack < 0 } then { puts $failure } else { puts $success } } } close $STF # Execute the script in SmarTtime if { [ catch {run_tool -name "VERIFYTIMING" -script $filename} ] } then { puts "\n\nUnexpected error encountered while running the script. Please contact Microsemi Tech Support.\n\n" } # Remove temporary file file delete $filename # Regenerating timing reports catch {run_tool -name "VERIFYTIMING"} }