#Build: Synplify Pro F-2012.03M-SP2-SF2 , Build 129R, Aug 12 2012
#install: C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2
#OS: Windows XP 5.1
#Hostname: ANDREY2

#Implementation: synthesis

$ Start of Compile
#Mon Feb 04 16:14:03 2013

Synopsys Verilog Compiler, version comp201203rcp1, Build 129R, built Aug 12 2012
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\generic\smartfusion2.v"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\umr_capim.v"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\scemi_pipes.svh"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\hypermods.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\SgCore\CCC\2.0.005\ccc_comps.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\CCC_0\g4m_system_CCC_0_CCC.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\DirectCore\CoreSF2Config\0.1.6\rtl\vlog\core\coresf2config.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\DirectCore\CoreSF2Reset\0.1.6\rtl\vlog\core\coresf2reset.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\SgCore\OSC\0.0.502\osc_comps.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\FABOSC_0\g4m_system_FABOSC_0_OSC.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_MSS\g4m_system_MSS_tmp_syn.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_MSS\g4m_system_MSS.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\g4m_system.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_top\g4m_system_top.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module g4m_system_top
@N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF

@N:CG364 : smartfusion2.v(371) | Synthesizing module VCC

@N:CG364 : smartfusion2.v(367) | Synthesizing module GND

@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

@N:CG364 : ccc_comps.v(2) | Synthesizing module CCC

@N:CG364 : g4m_system_CCC_0_CCC.v(5) | Synthesizing module g4m_system_CCC_0_CCC

@N:CG364 : coresf2config.v(21) | Synthesizing module CoreSF2Config

@N:CG364 : coresf2reset.v(22) | Synthesizing module CoreSF2Reset

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000011
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	COUNT_130us=32'b00000000000000000001100101100100
	COUNT_DDR=32'b00000000000000000010011100010000
	COUNT_MAX=32'b00000000000000000010011100010000
	COUNT_WIDTH=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreSF2Reset_Z1

@N:CL177 : coresf2reset.v(402) | Sharing sequential element sdif0_spll_lock_q1.
@N:CL177 : coresf2reset.v(402) | Sharing sequential element fpll_lock_q1.
@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

@N:CG364 : osc_comps.v(23) | Synthesizing module XTLOSC

@N:CG364 : g4m_system_FABOSC_0_OSC.v(5) | Synthesizing module g4m_system_FABOSC_0_OSC

@N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF

@N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF

@N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

@N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

@N:CG364 : g4m_system_MSS_tmp_syn.v(5) | Synthesizing module MSS_050

@N:CG364 : g4m_system_MSS.v(9) | Synthesizing module g4m_system_MSS

@N:CG364 : smartfusion2.v(741) | Synthesizing module SYSRESET

@N:CG364 : g4m_system.v(9) | Synthesizing module g4m_system

@N:CG364 : g4m_system_top.v(9) | Synthesizing module g4m_system_top

@W:CL157 : g4m_system_FABOSC_0_OSC.v(18) | *Output RCOSC_25_50MHZ_MSS has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(19) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(21) | *Output RCOSC_1MHZ_MSS has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(22) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(23) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(24) | *Output XTLOSC_MSS has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(26) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@N:CL177 : coresf2reset.v(402) | Sharing sequential element fpll_lock_q2.
@N:CL177 : coresf2reset.v(402) | Sharing sequential element sdif0_spll_lock_q2.
@N:CL201 : coresf2reset.v(656) | Trying to extract state machine for register sm2_state
Extracted state machine for register sm2_state
State machine has 2 reachable states with original encodings of:
   000
   001
@N:CL201 : coresf2reset.v(608) | Trying to extract state machine for register sm1_state
Extracted state machine for register sm1_state
State machine has 2 reachable states with original encodings of:
   000
   001
@N:CL201 : coresf2reset.v(517) | Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : coresf2reset.v(49) | Input FPLL_LOCK is unused
@W:CL159 : coresf2reset.v(52) | Input SDIF0_SPLL_LOCK is unused
@W:CL159 : coresf2reset.v(56) | Input SDIF1_SPLL_LOCK is unused
@N:CL201 : coresf2config.v(293) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Feb 04 16:14:03 2013

###########################################################]

Premap Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 768R, Built Aug 13 2012 09:36:57 Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2012.03M-SP2-SF2 Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Reading constraint file: C:\Actelprj\M2S-SOM-2A\constraint\g4m_system_top_synthesis.sdc Linked File: g4m_system_top_scck.rpt Printing clock summary report in "C:\Actelprj\M2S-SOM-2A\synthesis\g4m_system_top_scck.rpt" file @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @N:MF547 : | Generated clock conversion disabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB) Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB) Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB) @W:BN132 : coresf2reset.v(517) | Removing sequential instance SDIF1_CORE_RESET_N, because it is equivalent to instance SDIF0_CORE_RESET_N @W:BN132 : coresf2reset.v(608) | Removing sequential instance MSS_RESET_N_F2M, because it is equivalent to instance M3_RESET_N @W:BN132 : coresf2reset.v(517) | Removing sequential instance SDIF1_PHY_RESET_N, because it is equivalent to instance SDIF0_PHY_RESET_N @W:BN132 : coresf2reset.v(517) | Removing sequential instance MDDR_DDR_AXI_S_CORE_RESET_N, because it is equivalent to instance FDDR_CORE_RESET_N Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------ System 1.0 MHz 1000.000 system system_clkgroup GL0_net_inferred_clock 83.0 MHz 12.048 declared Inferred_clkgroup_0 50_MHz_RC_Clock 50.0 MHz 20.000 declared Inferred_clkgroup_1 FIC_2_APB_M_PCLK_inferred_clock 41.5 MHz 24.096 declared Inferred_clkgroup_2 MAC_MII_RX_CLK 25.0 MHz 40.000 declared MAC_Clocks MAC_MII_TX_CLK 25.0 MHz 40.000 declared MAC_Clocks ================================================================================================ syn_allowed_resources : blockrams=69 set on top level netlist g4m_system_top Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 72MB) @N:BN225 : | Writing default property annotation file C:\Actelprj\M2S-SOM-2A\synthesis\g4m_system_top.sap. Pre-mapping successful! At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 04 16:14:04 2013 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 768R, Built Aug 13 2012 09:36:57 Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2012.03M-SP2-SF2 Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @N:MF547 : | Generated clock conversion disabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 49MB) Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 51MB) Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 71MB) @W:MO111 : g4m_system_fabosc_0_osc.v(26) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO111 : g4m_system_fabosc_0_osc.v(24) | Tristate driver XTLOSC_MSS on net XTLOSC_MSS has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO111 : g4m_system_fabosc_0_osc.v(23) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO111 : g4m_system_fabosc_0_osc.v(22) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO111 : g4m_system_fabosc_0_osc.v(21) | Tristate driver RCOSC_1MHZ_MSS on net RCOSC_1MHZ_MSS has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO111 : g4m_system_fabosc_0_osc.v(19) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO111 : g4m_system_fabosc_0_osc.v(18) | Tristate driver RCOSC_25_50MHZ_MSS on net RCOSC_25_50MHZ_MSS has its enable tied to GND (module g4m_system_FABOSC_0_OSC) @W:MO171 : coresf2reset.v(317) | Sequential instance CORESF2RESET_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:BN132 : coresf2reset.v(331) | Removing sequential instance g4m_system_0.CORESF2RESET_0.sm2_areset_n_q1, because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm0_areset_n_q1 @W:BN132 : coresf2reset.v(331) | Removing sequential instance g4m_system_0.CORESF2RESET_0.sm2_areset_n_rcosc, because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm0_areset_n_rcosc Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Encoding state machine state[2:0] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[31], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[30] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[30], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[29] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[29], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[28] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[28], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[27] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[27], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[26] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[26], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[25] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[25], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[24] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[24], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[23] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[23], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[22] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[22], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[21] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[21], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[20] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[20], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[19] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[19], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[18] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[18], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[17] @W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[17], because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[16] @N:BN362 : coresf2config.v(370) | Removing sequential instance FIC_2_APB_M_PRDATA[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(370) | Boundary register FIC_2_APB_M_PRDATA[16] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Encoding state machine sm0_state[6:0] (netlist:statemachine) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sm2_state[1:0] (netlist:statemachine) original code -> new code 000 -> 0 001 -> 1 Encoding state machine sm1_state[1:0] (netlist:statemachine) original code -> new code 000 -> 0 001 -> 1 @W:MO129 : coresf2reset.v(608) | Sequential instance g4m_system_0.CORESF2RESET_0.sm1_state[0] reduced to a combinational gate by constant propagation @N: : coresf2reset.v(674) | Found counter in view:work.CoreSF2Reset_Z1(verilog) inst count[13:0] @W:BN132 : coresf2reset.v(402) | Removing sequential instance g4m_system_0.CORESF2RESET_0.sdif1_spll_lock_q1, because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm2_state[0] @N:BN362 : coresf2reset.v(608) | Removing sequential instance M3_RESET_N in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs @W:BN132 : coresf2reset.v(517) | Removing instance g4m_system_0.CORESF2RESET_0.USER_FAB_RESET_N, because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm0_state[6] @N:BN362 : coresf2reset.v(517) | Removing sequential instance g4m_system_0.CORESF2RESET_0.FDDR_CORE_RESET_N in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(517) | Removing sequential instance g4m_system_0.CORESF2RESET_0.SDIF0_CORE_RESET_N in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(517) | Removing sequential instance g4m_system_0.CORESF2RESET_0.SDIF0_PHY_RESET_N in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[14] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[14] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[11] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[11] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[31] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[31] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[30] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[30] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[29] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[29] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[28] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[28] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[27] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[27] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[26] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[26] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[25] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[25] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[24] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[24] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[23] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[23] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[22] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[22] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[21] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[21] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[20] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[20] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[19] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[19] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[18] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[18] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[17] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[17] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[16] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs @A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[16] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 72MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N:FP130 : | Promoting Net g4m_system_0.g4m_system_MSS_0.FIC_2_APB_M_PCLK_i on CLKINT I_4 @N:FP130 : | Promoting Net g4m_system_0.CORESF2CONFIG_0_APB_S_PRESET_N on CLKINT I_5 @N:FP130 : | Promoting Net g4m_system_0.CORESF2RESET_0.sm2_areset_n_rcosc on CLKINT I_6 Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Writing Analyst data base C:\Actelprj\M2S-SOM-2A\synthesis\g4m_system_top.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 71MB peak: 72MB) Writing EDIF Netlist and constraint files F-2012.03M-SP2-SF2 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 72MB peak: 73MB) @W:MT246 : g4m_system.v(582) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : g4m_system_fabosc_0_osc.v(34) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : g4m_system_fabosc_0_osc.v(32) | Blackbox RCOSC_25_50MHZ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : g4m_system_fabosc_0_osc.v(30) | Blackbox RCOSC_25_50MHZ_FAB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : g4m_system_ccc_0_ccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock MAC_MII_RX_CLK with period 40.00ns Found clock MAC_MII_TX_CLK with period 40.00ns Found clock FIC_2_APB_M_PCLK_inferred_clock with period 24.10ns Found clock 50_MHz_RC_Clock with period 20.00ns Found clock GL0_net_inferred_clock with period 12.05ns ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Feb 04 16:14:06 2013 # Top view: g4m_system_top Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\Actelprj\M2S-SOM-2A\constraint\g4m_system_top_synthesis.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 8.718 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------- 50_MHz_RC_Clock 50.0 MHz 339.0 MHz 20.000 2.950 17.050 declared Inferred_clkgroup_1 FIC_2_APB_M_PCLK_inferred_clock 41.5 MHz 150.1 MHz 24.096 6.661 8.718 declared Inferred_clkgroup_2 GL0_net_inferred_clock 83.0 MHz NA 12.048 NA NA declared Inferred_clkgroup_0 MAC_MII_RX_CLK 25.0 MHz NA 40.000 NA NA declared MAC_Clocks MAC_MII_TX_CLK 25.0 MHz NA 40.000 NA NA declared MAC_Clocks System 100.0 MHz 5086.5 MHz 10.000 0.197 9.803 system system_clkgroup ======================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 9.803 | No paths - | No paths - | No paths - GL0_net_inferred_clock FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - 50_MHz_RC_Clock 50_MHz_RC_Clock | 20.000 17.050 | No paths - | No paths - | No paths - 50_MHz_RC_Clock FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FIC_2_APB_M_PCLK_inferred_clock GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FIC_2_APB_M_PCLK_inferred_clock 50_MHz_RC_Clock | Diff grp - | No paths - | No paths - | No paths - FIC_2_APB_M_PCLK_inferred_clock FIC_2_APB_M_PCLK_inferred_clock | 24.096 20.729 | No paths - | 12.048 9.882 | 12.048 8.718 ========================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: 50_MHz_RC_Clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------- g4m_system_0.CORESF2RESET_0.count[0] 50_MHz_RC_Clock SLE Q count[0] 0.091 17.050 g4m_system_0.CORESF2RESET_0.count[5] 50_MHz_RC_Clock SLE Q count[5] 0.091 17.179 g4m_system_0.CORESF2RESET_0.count[1] 50_MHz_RC_Clock SLE Q count[1] 0.091 17.397 g4m_system_0.CORESF2RESET_0.count[2] 50_MHz_RC_Clock SLE Q count[2] 0.114 17.433 g4m_system_0.CORESF2RESET_0.count[6] 50_MHz_RC_Clock SLE Q count[6] 0.091 17.438 g4m_system_0.CORESF2RESET_0.count[3] 50_MHz_RC_Clock SLE Q count[3] 0.091 17.483 g4m_system_0.CORESF2RESET_0.sm0_state[5] 50_MHz_RC_Clock SLE Q sm0_state[5] 0.114 17.483 g4m_system_0.CORESF2RESET_0.count[4] 50_MHz_RC_Clock SLE Q count[4] 0.091 17.500 g4m_system_0.CORESF2RESET_0.count[11] 50_MHz_RC_Clock SLE Q count[11] 0.091 17.525 g4m_system_0.CORESF2RESET_0.count[7] 50_MHz_RC_Clock SLE Q count[7] 0.091 17.529 ===================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------- g4m_system_0.CORESF2RESET_0.count_130us 50_MHz_RC_Clock SLE EN count_130us4 19.647 17.050 g4m_system_0.CORESF2RESET_0.count_ddr 50_MHz_RC_Clock SLE EN count_ddr4 19.647 17.179 g4m_system_0.CORESF2RESET_0.count_enable 50_MHz_RC_Clock SLE EN un1_next_init_done_rcosc_0_sqmuxa_0 19.647 17.483 g4m_system_0.CORESF2RESET_0.sm0_state[3] 50_MHz_RC_Clock SLE D sm0_state_ns[3] 19.733 17.660 g4m_system_0.CORESF2RESET_0.INIT_DONE 50_MHz_RC_Clock SLE D init_done_rcosc_0_sqmuxa 19.733 17.732 g4m_system_0.CORESF2RESET_0.sm0_state[4] 50_MHz_RC_Clock SLE D sm0_state_ns[4] 19.733 18.107 g4m_system_0.CORESF2RESET_0.sm0_state[5] 50_MHz_RC_Clock SLE D sm0_state_ns[5] 19.733 18.144 g4m_system_0.CORESF2RESET_0.sm0_state[6] 50_MHz_RC_Clock SLE EN next_init_done_rcosc_0_sqmuxa 19.647 18.267 g4m_system_0.CORESF2RESET_0.count_enable 50_MHz_RC_Clock SLE D next_sdif0_phy_reset_n_0_sqmuxa 19.733 18.305 g4m_system_0.CORESF2RESET_0.sm0_state[2] 50_MHz_RC_Clock SLE D sm0_state_ns[2] 19.733 18.322 ============================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.353 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.647 - Propagation time: 2.597 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.050 Number of logic level(s): 2 Starting point: g4m_system_0.CORESF2RESET_0.count[0] / Q Ending point: g4m_system_0.CORESF2RESET_0.count_130us / EN The start point is clocked by 50_MHz_RC_Clock [rising] on pin CLK The end point is clocked by 50_MHz_RC_Clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- g4m_system_0.CORESF2RESET_0.count[0] SLE Q Out 0.091 0.091 - count[0] Net - - 0.574 - 3 g4m_system_0.CORESF2RESET_0.count_130us4_7 CFG4 D In - 0.666 - g4m_system_0.CORESF2RESET_0.count_130us4_7 CFG4 Y Out 0.496 1.162 - count_ddr4_7 Net - - 0.378 - 2 g4m_system_0.CORESF2RESET_0.count_130us4 CFG4 D In - 1.540 - g4m_system_0.CORESF2RESET_0.count_130us4 CFG4 Y Out 0.493 2.033 - count_130us4 Net - - 0.564 - 1 g4m_system_0.CORESF2RESET_0.count_130us SLE EN In - 2.597 - ========================================================================================================= Total path delay (propagation time + setup) of 2.950 is 1.434(48.6%) logic and 1.516(51.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------- g4m_system_0.CORESF2CONFIG_0.psel FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.114 8.718 g4m_system_0.CORESF2CONFIG_0.state[1] FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.091 9.882 g4m_system_0.CORESF2CONFIG_0.state[0] FIC_2_APB_M_PCLK_inferred_clock SLE Q state[0] 0.091 10.318 g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[15] FIC_2_APB_M_PCLK_inferred_clock SLE Q CORESF2CONFIG_0_MDDR_APBmslave_PADDR[15] 0.091 20.729 g4m_system_0.CORESF2CONFIG_0.CLR_INIT_DONE FIC_2_APB_M_PCLK_inferred_clock SLE Q CORESF2CONFIG_0_CLR_INIT_DONE 0.114 21.044 g4m_system_0.CORESF2CONFIG_0.CONFIG_DONE FIC_2_APB_M_PCLK_inferred_clock SLE Q CORESF2CONFIG_0_CONFIG_DONE 0.114 21.091 g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[13] FIC_2_APB_M_PCLK_inferred_clock SLE Q CORESF2CONFIG_0_MDDR_APBmslave_PADDR[13] 0.114 21.366 g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[12] FIC_2_APB_M_PCLK_inferred_clock SLE Q CORESF2CONFIG_0_MDDR_APBmslave_PADDR[12] 0.114 21.532 g4m_system_0.CORESF2CONFIG_0.INIT_DONE_q2 FIC_2_APB_M_PCLK_inferred_clock SLE Q INIT_DONE_q2 0.091 21.684 g4m_system_0.CORESF2CONFIG_0.INIT_DONE_q3 FIC_2_APB_M_PCLK_inferred_clock SLE Q INIT_DONE_q3 0.114 22.509 ======================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------- g4m_system_0.CORESF2CONFIG_0.CLR_INIT_DONE FIC_2_APB_M_PCLK_inferred_clock SLE EN N_5 11.695 8.718 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PREADY FIC_2_APB_M_PCLK_inferred_clock SLE EN N_9_i_0 11.695 9.338 g4m_system_0.CORESF2CONFIG_0.state[1] FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 11.781 9.356 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[0] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 11.781 9.403 g4m_system_0.CORESF2CONFIG_0.CONFIG_DONE FIC_2_APB_M_PCLK_inferred_clock SLE EN control_reg_14 11.695 9.481 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[1] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[1] 11.781 9.494 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[2] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 11.781 9.494 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[3] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 11.781 9.494 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[4] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 11.781 9.494 g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[5] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 11.781 9.494 ================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.048 - Setup time: 0.353 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.695 - Propagation time: 2.978 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 8.718 Number of logic level(s): 3 Starting point: g4m_system_0.CORESF2CONFIG_0.psel / Q Ending point: g4m_system_0.CORESF2CONFIG_0.CLR_INIT_DONE / EN The start point is clocked by FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- g4m_system_0.CORESF2CONFIG_0.psel SLE Q Out 0.114 0.114 - psel Net - - 0.574 - 3 g4m_system_0.CORESF2CONFIG_0.control_reg_29_0_a3 CFG2 A In - 0.688 - g4m_system_0.CORESF2CONFIG_0.control_reg_29_0_a3 CFG2 Y Out 0.091 0.779 - N_64 Net - - 0.378 - 2 g4m_system_0.CORESF2CONFIG_0.control_reg_29_0_a2 CFG4 D In - 1.158 - g4m_system_0.CORESF2CONFIG_0.control_reg_29_0_a2 CFG4 Y Out 0.493 1.651 - control_reg_29 Net - - 0.591 - 2 g4m_system_0.CORESF2CONFIG_0.control_reg_2_1_sqmuxa_i_s CFG3 B In - 2.242 - g4m_system_0.CORESF2CONFIG_0.control_reg_2_1_sqmuxa_i_s CFG3 Y Out 0.172 2.414 - N_5 Net - - 0.564 - 1 g4m_system_0.CORESF2CONFIG_0.CLR_INIT_DONE SLE EN In - 2.978 - ====================================================================================================================== Total path delay (propagation time + setup) of 3.331 is 1.224(36.7%) logic and 2.107(63.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------- g4m_system_0.FABOSC_0.I_RCOSC_25_50MHZ System RCOSC_25_50MHZ CLKOUT N_RCOSC_25_50MHZ_CLKOUT 0.000 9.803 g4m_system_0.FABOSC_0.I_XTLOSC System XTLOSC CLKOUT FABOSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 0.000 9.803 =============================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------- g4m_system_0.CCC_0.CCC_INST System CCC XTLOSC FABOSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 10.000 9.803 g4m_system_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB System RCOSC_25_50MHZ_FAB A N_RCOSC_25_50MHZ_CLKOUT 10.000 9.803 ======================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 0.197 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 9.803 Number of logic level(s): 0 Starting point: g4m_system_0.FABOSC_0.I_RCOSC_25_50MHZ / CLKOUT Ending point: g4m_system_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB / A The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- g4m_system_0.FABOSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ CLKOUT Out 0.000 0.000 - N_RCOSC_25_50MHZ_CLKOUT Net - - 0.197 - 1 g4m_system_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB RCOSC_25_50MHZ_FAB A In - 0.197 - ========================================================================================================================= Total path delay (propagation time + setup) of 0.197 is 0.000(0.0%) logic and 0.197(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for g4m_system_top Mapping to part: m2s050tfbga896std Cell usage: CCC 1 use CLKINT 4 uses MSS_050 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use XTLOSC 1 use CFG1 2 uses CFG2 26 uses CFG3 9 uses CFG4 17 uses Carry primitives used for arithmetic functions: ARI1 14 uses Sequential Cells: SLE 91 uses Latch bits not including I/Os: 91 (0%) DSP Blocks: 0 I/O ports: 104 I/O primitives: 101 BIBUF 38 uses INBUF 17 uses OUTBUF 40 uses OUTBUF_DIFF 1 use TRIBUFF 5 uses Global Clock Buffers: 4 Total LUTs: 54 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 24MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 04 16:14:06 2013 ###########################################################]