#Build: Synplify Pro 8.5F, Build 001R, Mar 7 2006 #install: D:\Libero72\Synplify\Synplify_85F #OS: Windows XP 5.1 #Hostname: WXP-WONGAL #Thu Feb 08 18:47:06 2007 $ Running Identify Instrumentor. See log file: @N: : identify.log | #Thu Feb 08 18:47:06 2007 $ Start of Compile #Thu Feb 08 18:47:13 2007 Synplicity VHDL Compiler, version 3.4.1, Build 137R, built Apr 7 2006 Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved @N: : config_top.vhd(23) | Top entity is set to config_top. VHDL syntax check successful! Options changed - recompiling @N:CD630 : config_top.vhd(17) | Synthesizing work.config_top.rtl @N:CD630 : syn_dics.vhd(2118) | Synthesizing work.iice_0.structure @N:CD630 : syn_dics.vhd(1590) | Synthesizing work.b7_ofwnt9s.b3_vfw @N:CD630 : syn_dics.vhd(1232) | Synthesizing work.b12_ofwnt9_wmeed.b3_joc Post processing for work.b12_ofwnt9_wmeed.b3_joc @N:CD630 : syn_dics.vhd(1523) | Synthesizing work.ram_block.struct @N:CD630 : syn_dics.vhd(1442) | Synthesizing work.ramsliceram_block.struct @N:CD630 : syn_dics.vhd(1290) | Synthesizing work.genericramram_block.struct @N:CD630 : fusion.vhd(3267) | Synthesizing work.ram512x18.syn_black_box Post processing for work.ram512x18.syn_black_box Post processing for work.genericramram_block.struct Post processing for work.ramsliceram_block.struct Post processing for work.ram_block.struct Post processing for work.b7_ofwnt9s.b3_vfw @N:CD630 : syn_dics.vhd(1855) | Synthesizing work.b3_ukr.b3_vcj @N:CD630 : syn_dics.vhd(1759) | Synthesizing work.b7_plf_6ln.b3_vcj Post processing for work.b7_plf_6ln.b3_vcj @N:CD630 : syn_dics.vhd(1804) | Synthesizing work.b12_nvmfl_la1xyh.b3_vcj Post processing for work.b12_nvmfl_la1xyh.b3_vcj Post processing for work.b3_ukr.b3_vcj @N:CD630 : syn_dics.vhd(1955) | Synthesizing work.b3_12m.b6_oczobx @W:CD638 : syn_dics.vhd(2019) | Signal b11_nutz3qm_tkl is undriven @N:CD630 : syn_dics.vhd(732) | Synthesizing work.b7_pffzrny.b6_oczobx @N:CD630 : syn_dics.vhd(492) | Synthesizing work.b5_nvmfl.b6_oczobx Post processing for work.b5_nvmfl.b6_oczobx @N:CD630 : syn_dics.vhd(645) | Synthesizing work.b11_psyil9s1fkt.b3_joc @N:CD630 : syn_dics.vhd(468) | Synthesizing work.b11_jfjtlvyy9qh.b3_joc Post processing for work.b11_jfjtlvyy9qh.b3_joc @N:CD630 : syn_dics.vhd(538) | Synthesizing work.b15_crgctcua_eh4_20.b3_joc @N:CD630 : syn_dics.vhd(526) | Synthesizing work.b9_o2yyf_fg2.b3_joc Post processing for work.b9_o2yyf_fg2.b3_joc Post processing for work.b15_crgctcua_eh4_20.b3_joc @N:CD630 : syn_dics.vhd(412) | Synthesizing work.b8_1lbcqdr1.b3_joc Post processing for work.b8_1lbcqdr1.b3_joc @N:CD630 : syn_dics.vhd(606) | Synthesizing work.b13_crgctcua_xf_c.b3_joc @N:CD630 : syn_dics.vhd(594) | Synthesizing work.b8_o2yyf_ye.b3_joc Post processing for work.b8_o2yyf_ye.b3_joc Post processing for work.b13_crgctcua_xf_c.b3_joc @N:CD630 : syn_dics.vhd(380) | Synthesizing work.b7_yfjnjcp.b3_joc Post processing for work.b7_yfjnjcp.b3_joc Post processing for work.b11_psyil9s1fkt.b3_joc Post processing for work.b7_pffzrny.b6_oczobx @W:CL234 : syn_dics.vhd(734) | Input port bits <0 to 1> of b9_slyy_nrgd(0 to 52) are unused @W:CL234 : syn_dics.vhd(734) | Input port bits <3 to 5> of b9_slyy_nrgd(0 to 52) are unused @W:CL234 : syn_dics.vhd(734) | Input port bits <28 to 30> of b9_slyy_nrgd(0 to 52) are unused @W:CL234 : syn_dics.vhd(734) | Input port bits <35 to 37> of b9_slyy_nrgd(0 to 52) are unused @W:CL234 : syn_dics.vhd(734) | Input port bits <46 to 48> of b9_slyy_nrgd(0 to 52) are unused @N:CD630 : syn_dics.vhd(934) | Synthesizing work.b7_ocbylxc.b3_joc @W:CD274 : syn_dics.vhd(1050) | Incomplete case statement - add more cases or a when others @N:CD630 : syn_dics.vhd(845) | Synthesizing work.b8_nr_ymqrg.b3_joc Post processing for work.b8_nr_ymqrg.b3_joc Post processing for work.b7_ocbylxc.b3_joc @N:CL201 : syn_dics.vhd(1032) | Trying to extract state machine for register b13_nAzGfFM_sLsv3 Extracted state machine for register b13_nAzGfFM_sLsv3 State machine has 14 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Post processing for work.b3_12m.b6_oczobx Post processing for work.iice_0.structure @N:CD630 : syn_dics.vhd(2062) | Synthesizing work.ldic1_0.structure Post processing for work.ldic1_0.structure @N:CD630 : syn_dics.vhd(243) | Synthesizing work.comm_block.b3_joc @N:CD630 : syn_dics.vhd(5) | Synthesizing work.b9_orbiwxaef.b3_vcj Post processing for work.b9_orbiwxaef.b3_vcj @N:CD630 : syn_dics.vhd(192) | Synthesizing work.b16_rcmi_qlx9_yhpm7y.b3_vcj Post processing for work.b16_rcmi_qlx9_yhpm7y.b3_vcj @N:CD630 : syn_dics.vhd(70) | Synthesizing work.jtag_interface.b3_vcj @W:CD434 : syn_dics.vhd(159) | Signal identify_clk2_no_clk_buffer_needed in the sensitivity list is not used in the process @W:CD434 : syn_dics.vhd(170) | Signal identify_clk2_no_clk_buffer_needed in the sensitivity list is not used in the process @W:CD638 : syn_dics.vhd(94) | Signal b14_gir9p_al2ezh2v is undriven @N:CD630 : fusion.vhd(4363) | Synthesizing work.ujtag.syn_black_box Post processing for work.ujtag.syn_black_box Post processing for work.jtag_interface.b3_vcj Post processing for work.comm_block.b3_joc @N:CD630 : cfgnvm.vhd(7) | Synthesizing work.cfgnvm.def_arch @N:CD630 : fusion.vhd(4474) | Synthesizing work.nvm.syn_black_box Post processing for work.nvm.syn_black_box @N:CD630 : fusion.vhd(3021) | Synthesizing work.vcc.syn_black_box Post processing for work.vcc.syn_black_box @N:CD630 : fusion.vhd(1901) | Synthesizing work.gnd.syn_black_box Post processing for work.gnd.syn_black_box Post processing for work.cfgnvm.def_arch @W:CL168 : cfgnvm.vhd(119) | Pruning instance VCC_power_inst1 - not in use ... @N:CD630 : sconfig.vhd(18) | Synthesizing work.sconfig.rtl @N:CD630 : syn_dics.vhd(2087) | Synthesizing work.ldic4_0.structure Post processing for work.ldic4_0.structure @N:CD630 : ram256x8.vhd(7) | Synthesizing work.ram256x8.def_arch @N:CD630 : fusion.vhd(3184) | Synthesizing work.ram4k9.syn_black_box Post processing for work.ram4k9.syn_black_box @N:CD630 : fusion.vhd(2119) | Synthesizing work.inv.syn_black_box Post processing for work.inv.syn_black_box Post processing for work.ram256x8.def_arch Post processing for work.sconfig.rtl @W:CL170 : sconfig.vhd(361) | Pruning bit <7> of wdata(7 downto 0) - not in use ... @N:CL201 : sconfig.vhd(541) | Trying to extract state machine for register state2 Extracted state machine for register state2 State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @N:CL201 : sconfig.vhd(233) | Trying to extract state machine for register state Extracted state machine for register state State machine has 8 reachable states with original encodings of: 000 001 010 011 100 101 110 111 @N:CD630 : pll_60_40_10.vhd(7) | Synthesizing work.pll_60_40_10.def_arch @N:CD630 : fusion.vhd(4213) | Synthesizing work.pll.syn_black_box Post processing for work.pll.syn_black_box Post processing for work.pll_60_40_10.def_arch @N:CD630 : rc_osc.vhd(7) | Synthesizing work.rc_osc.def_arch @N:CD630 : fusion.vhd(4457) | Synthesizing work.rcosc.syn_black_box Post processing for work.rcosc.syn_black_box Post processing for work.rc_osc.def_arch Post processing for work.config_top.rtl @END Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Thu Feb 08 18:47:15 2007 ###########################################################[ Synplicity Proasic Technology Mapper, Version 8.6.0, Build 155R, Built Apr 11 2006 Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved Version 8.5F @N:MF249 : | Running in 32-bit mode. @N: : | Gated clock conversion disabled @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking @W:BN154 : | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed Automatic dissolve at startup in view:work.sconfig(rtl) of ldic4_inst_0(ldic4_0) Automatic dissolve at startup in view:work.sconfig(rtl) of M1(ram256x8) Automatic dissolve at startup in view:work.comm_block(b3_joc) of b9_ORb_xNywD(b9_ORbIwXaEF) Automatic dissolve at startup in view:work.comm_block(b3_joc) of b7_Rcmi_ql(b16_Rcmi_qlx9_yHpm7y) Automatic dissolve at startup in view:work.b7_OCByLXC(b3_joc) of b11_nUTGT_khWqH(b8_nR_ymqrG) Automatic dissolve at startup in view:work.b13_CRGcTCua_xF_C(b3_joc) of b6_d_FG_R.0.b24_O2yyf_yE_yMuR3Qy_P_4rZRf(b8_O2yyf_yE) Automatic dissolve at startup in view:work.b13_CRGcTCua_xF_C(b3_joc) of b6_d_FG_H.1.b24_O2yyf_yE_yMuR3Qy_O_4rZRf(b8_O2yyf_yE) Automatic dissolve at startup in view:work.b13_CRGcTCua_xF_C(b3_joc) of b6_d_FG_H.0.b24_O2yyf_yE_yMuR3Qy_O_4rZRf(b8_O2yyf_yE) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_G.0.b25_O2yyf_fG2_MiQA1E6_h_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_e.0.b25_O2yyf_fG2_MiQA1E6_r_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_e.2.b25_O2yyf_fG2_MiQA1E6_r_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_e.1.b25_O2yyf_fG2_MiQA1E6_r_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.3.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.0.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.2.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.7.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.4.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.1.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.6.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.8.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b15_CRGcTCua_eH4_20(b3_joc) of b7_d_mIC_J.5.b25_O2yyf_fG2_MiQA1E6_q_lnxob(b9_O2yyf_fG2) Automatic dissolve at startup in view:work.b11_PSyil9s1fkT(b3_joc) of b9_jZntTquwF(b11_jFJtLvYY9qh) Automatic dissolve at startup in view:work.b7_PfFzrNY(b6_oczobx) of b5_PbrtL(b5_nvmFL) Automatic dissolve at startup in view:work.ramSliceram_block(struct) of GenericRAMInst3(GenericRAMram_block) Automatic dissolve at startup in view:work.ramSliceram_block(struct) of GenericRAMInst2(GenericRAMram_block) Automatic dissolve at startup in view:work.ramSliceram_block(struct) of GenericRAMInst1(GenericRAMram_block) Automatic dissolve at startup in view:work.ramSliceram_block(struct) of GenericRAMInst0(GenericRAMram_block) Automatic dissolve at startup in view:work.config_top(rtl) of ldic1_inst_0(ldic1_0) Automatic dissolve at startup in view:work.config_top(rtl) of M2(cfgnvm) Automatic dissolve at startup in view:work.config_top(rtl) of M1(cfgnvm) Automatic dissolve at startup in view:work.config_top(rtl) of C2(PLL_60_40_10) Automatic dissolve at startup in view:work.config_top(rtl) of C1(rc_osc) RTL optimization done. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 29MB peak: 30MB) Encoding state machine work.sconfig(rtl)-state[0:7] original code -> new code 000 -> 00000001 001 -> 00000010 010 -> 00000100 011 -> 00001000 100 -> 00010000 101 -> 00100000 110 -> 01000000 111 -> 10000000 Encoding state machine work.sconfig(rtl)-state2[0:9] original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 @N:MF176 : | Default generator successful @N:MF238 : sconfig.vhd(288) | Found 19 bit incrementor, 'un1_inc[18:0]' @N:MF176 : | Default generator successful Encoding state machine work.b7_OCByLXC(b3_joc)-b13_nAzGfFM_sLsv3[0:13] original code -> new code 0000 -> 00000000000001 0001 -> 00000000000010 0010 -> 00000000000100 0011 -> 00000000001000 0100 -> 00000000010000 0101 -> 00000000100000 0110 -> 00000001000000 0111 -> 00000010000000 1000 -> 00000100000000 1001 -> 00001000000000 1010 -> 00010000000000 1011 -> 00100000000000 1100 -> 01000000000000 1101 -> 10000000000000 @W:MO129 : | Sequential instance iice_inst_0.b7_12mFLWM.b5_nUTGT.b3_nfs[1] has been reduced to a combinational gate by constant propagation Finished factoring (Time elapsed 0h:00m:05s; Memory used current: 32MB peak: 33MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:05s; Memory used current: 32MB peak: 33MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:07s; Memory used current: 33MB peak: 34MB) Starting Early Timing Optimization (Time elapsed 0h:00m:07s; Memory used current: 34MB peak: 35MB) Finished Early Timing Optimization (Time elapsed 0h:00m:08s; Memory used current: 34MB peak: 35MB) @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.32.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[0] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.31.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[1] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.30.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[2] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.29.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[3] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.28.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[7] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.27.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[8] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.26.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[9] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.25.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[10] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.24.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[11] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.23.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[12] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.22.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[13] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.21.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[14] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.20.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[18] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.19.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[19] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.18.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[20] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.17.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[21] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.16.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[25] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.15.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[26] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.14.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[27] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.13.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[28] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.12.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[29] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.11.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[30] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.10.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[31] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.9.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[32] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.8.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[33] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.7.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[34] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.6.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[35] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.5.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[36] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.4.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[37] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.3.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[38] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.2.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[39] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.1.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[40] @W:BN132 : syn_dics.vhd(433) | Removing sequential instance iice_inst_0.b7_12mFLWM.b4_PfFz.b7_PbTtl9G.b5_7oBdQ.0.b6_1LbcgK.b11_uUG_C9CrTXy, because it is equivalent to instance iice_inst_0.b3_SoW.b8_OFWNT9LR[49] Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:08s; Memory used current: 33MB peak: 35MB) Finished preparing to map (Time elapsed 0h:00m:09s; Memory used current: 35MB peak: 35MB) Promoting Net b3_PK3 on CLKINT jtag_block.jtagi.b3_PK3_inferred_clock Promoting Net CLK_c on CLKBUF CLK_pad Promoting Net RST_c on CLKBUF RST_pad Promoting Net comm2iice_link_iice_0_a_0[7] on CLKINT I_75 Replicating nvm_addr_i_0[18], fanout 14 segments 2 Replicating U1.N_444, fanout 20 segments 2 Replicating U1.addr_ld_1_sqmuxa, fanout 17 segments 2 Replicating U1.addr_ld_0_sqmuxa, fanout 19 segments 2 Replicating U1.G1.0.P4.un12_state, fanout 19 segments 2 Buffering DI_c, fanout 27 segments 3 Buffering CSn_c, fanout 26 segments 3 Replicating U1.P6.un21_rstn, fanout 24 segments 2 Replicating U1.state2[1], fanout 22 segments 2 Replicating U1.state2[9], fanout 23 segments 2 Replicating U1.bit_cnt[2], fanout 13 segments 2 Replicating U1.bit_cnt[1], fanout 15 segments 2 Replicating U1.bit_cnt[0], fanout 20 segments 2 Replicating uplink_8_a[6], fanout 13 segments 2 Replicating uplink_8_a[9], fanout 14 segments 2 Replicating U1.P2.un6_bit_cnt, fanout 13 segments 2 Buffering CSn_c, fanout 13 segments 2 Replicating U1.state2[8], fanout 15 segments 2 Finished technology mapping (Time elapsed 0h:00m:10s; Memory used current: 34MB peak: 36MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:10s; Memory used current: 34MB peak: 36MB) Added 5 Buffers Added 15 Cells via replication Added 5 Buffers Added 15 Cells via replication Added 5 Buffers Added 15 Cells via replication Added 5 Buffers Added 15 Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:10s; Memory used current: 35MB peak: 36MB) @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking @W:BN153 : | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking @W:BN154 : | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed @N:BN191 : | Writing property annotation file D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify_2\config_top.tap. Writing Analyst data base D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify_2\config_top.srm @N:BN225 : | Writing default property annotation file D:\ProgrammingSRAM\sconfig\synthesis\rev_1_identify_2\config_top.map. Writing EDIF Netlist and constraint files Found clock config_top|CSn with period 1000.00ns Found clock config_top|CLK with period 1000.00ns Found clock jtag_interface|b3_PK3_inferred_clock with period 1000.00ns Found clock jtag_interface|b7_oSD_3vW_inferred_clock with period 1000.00ns Found clock jtag_interface|identify_clk2_no_clk_buffer_needed with period 1000.00ns @W: : pll_60_40_10.vhd(47) | Net mdic_link[5] appears to be a clock source which was not identified. Assuming default frequency. @W: : pll_60_40_10.vhd(47) | Net clk60M appears to be a clock source which was not identified. Assuming default frequency. ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Feb 08 18:47:30 2007 # Top view: config_top Library name: fusion Operating conditions: COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree ) Requested Frequency: 1.0 MHz Wire load mode: top Wire load model: fusion Paths requested: 5 Constraint File(s): @N:MT195 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT197 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 482.438 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------- config_top|CLK 1.0 MHz 28.5 MHz 1000.000 35.123 482.438 inferred Inferred_clkgroup_0 jtag_interface|b3_PK3_inferred_clock 1.0 MHz 24.0 MHz 1000.000 41.621 958.379 inferred Inferred_clkgroup_5 jtag_interface|b7_oSD_3vW_inferred_clock 1.0 MHz 73.1 MHz 1000.000 13.678 986.322 inferred Inferred_clkgroup_3 jtag_interface|identify_clk2_no_clk_buffer_needed 1.0 MHz 39.6 MHz 1000.000 25.274 974.726 inferred Inferred_clkgroup_4 System 1.0 MHz 31.7 MHz 1000.000 31.590 968.410 system default_clkgroup ========================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- config_top|CLK config_top|CLK | 1000.000 980.123 | 1000.000 981.249 | 500.000 482.439 | No paths - config_top|CLK config_top|CSn | Diff grp - | No paths - | No paths - | No paths - jtag_interface|b7_oSD_3vW_inferred_clock jtag_interface|b7_oSD_3vW_inferred_clock | 1000.000 986.322 | No paths - | No paths - | No paths - jtag_interface|b7_oSD_3vW_inferred_clock jtag_interface|identify_clk2_no_clk_buffer_needed | Diff grp - | No paths - | No paths - | No paths - jtag_interface|identify_clk2_no_clk_buffer_needed jtag_interface|identify_clk2_no_clk_buffer_needed | 1000.000 974.726 | No paths - | No paths - | No paths - jtag_interface|identify_clk2_no_clk_buffer_needed jtag_interface|b3_PK3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - jtag_interface|b3_PK3_inferred_clock jtag_interface|identify_clk2_no_clk_buffer_needed | Diff grp - | No paths - | No paths - | No paths - jtag_interface|b3_PK3_inferred_clock jtag_interface|b3_PK3_inferred_clock | 1000.000 958.379 | No paths - | No paths - | No paths - ================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: config_top|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------ U1.cmnd[5] config_top|CLK DFN1E1C1 Q uplink_8_a[14] 0.364 482.438 U1.cmnd[3] config_top|CLK DFN1E1C1 Q uplink_8_a[16] 0.364 482.843 U1.cmnd[6] config_top|CLK DFN1E1C1 Q uplink_8_a[13] 0.364 484.553 U1.cmnd[4] config_top|CLK DFN1E1C1 Q uplink_8_a[15] 0.364 484.766 U1.cmnd[1] config_top|CLK DFN1E1C1 Q uplink_8_a[18] 0.364 485.246 U1.cmnd[2] config_top|CLK DFN1E1C1 Q uplink_8_a[17] 0.364 485.253 U1.bit_cnt[0] config_top|CLK DFN1C1 Q bit_cnt[0] 0.364 485.992 U1.cmnd[0] config_top|CLK DFN1E1C1 Q uplink_8_a[19] 0.364 486.025 U1.bit_cnt[1] config_top|CLK DFN1C1 Q bit_cnt[1] 0.364 486.866 U1.bit_cnt[2] config_top|CLK DFN1C1 Q bit_cnt[2] 0.364 487.182 ================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------- U1.rdata[0] config_top|CLK DFN0C1 D rdata_4[0] 499.590 482.438 U1.rdata[1] config_top|CLK DFN0C1 D rdata_4[1] 499.590 482.438 U1.rdata[2] config_top|CLK DFN0C1 D rdata_4[2] 499.590 482.438 U1.rdata[3] config_top|CLK DFN0C1 D rdata_4[3] 499.590 482.438 U1.rdata[4] config_top|CLK DFN0C1 D rdata_4[4] 499.590 482.438 U1.rdata[5] config_top|CLK DFN0C1 D rdata_4[5] 499.590 482.447 U1.rdata[6] config_top|CLK DFN0C1 D rdata_4[6] 499.590 482.447 U1.rdata[7] config_top|CLK DFN0C1 D rdata_4[7] 499.590 482.447 U1.start[7] config_top|CLK DFN1C1 D start_3[7] 999.690 980.123 U1.start[6] config_top|CLK DFN1C1 D start_3[6] 999.690 981.046 ========================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 500.000 - Setup time: 0.410 = Required time: 499.590 - Propagation time: 17.152 = Slack (critical) : 482.439 Number of logic level(s): 5 Starting point: U1.cmnd[5] / Q Ending point: U1.rdata[0] / D The start point is clocked by config_top|CLK [rising] on pin CLK The end point is clocked by config_top|CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------- U1.cmnd[5] DFN1E1C1 Q Out 0.364 0.364 - uplink_8_a[14] Net - - 2.990 - 7 U1.un2_idis_1 NOR2 B In - 3.354 - U1.un2_idis_1 NOR2 Y Out 0.362 3.716 - un2_idis_1 Net - - 2.660 - 6 U1.un10_nxt0_2 NOR3A A In - 6.376 - U1.un10_nxt0_2 NOR3A Y Out 0.369 6.745 - nxt3_1 Net - - 2.990 - 7 U1.nxt3 NOR2B B In - 9.735 - U1.nxt3 NOR2B Y Out 0.351 10.086 - nvm_read Net - - 2.660 - 6 U1.P5.rdata_4_sn_m2 NOR2A B In - 12.746 - U1.P5.rdata_4_sn_m2 NOR2A Y Out 0.232 12.978 - N_591 Net - - 3.320 - 8 U1.P5.rdata_4[0] MX2C S In - 16.298 - U1.P5.rdata_4[0] MX2C Y Out 0.224 16.522 - rdata_4[0] Net - - 0.630 - 1 U1.rdata[0] DFN0C1 D In - 17.152 - ====================================================================================== Total path delay (propagation time + setup) of 17.561 is 2.311(13.2%) logic and 15.250(86.8%) route. ==================================== Detailed Report for Clock: jtag_interface|b3_PK3_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[9] 0.364 974.588 iice_inst_0.b3_SoW.b9_v_mzCDYXs[8] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[8] 0.364 974.886 iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[6] 0.364 975.530 iice_inst_0.b3_SoW.b9_v_mzCDYXs[7] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[7] 0.364 975.588 iice_inst_0.b3_SoW.b9_v_mzCDYXs[2] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[2] 0.364 975.591 iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[3] 0.364 975.649 iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[5] 0.364 976.523 iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[1] 0.364 976.584 iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[4] 0.364 976.584 iice_inst_0.b3_SoW.b9_v_mzCDYXs[0] jtag_interface|b3_PK3_inferred_clock DFN1 Q b9_v_mzCDYXs[0] 0.364 976.645 ======================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[7] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[7] 999.690 974.588 iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[9] 999.690 974.588 iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[6] 999.690 975.545 iice_inst_0.b3_SoW.b9_v_mzCDYXs[8] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[8] 999.690 975.545 iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[5] 999.690 975.975 iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[4] 999.690 976.932 iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[3] 999.690 978.202 iice_inst_0.b3_SoW.b9_v_mzCDYXs[2] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[2] 999.690 979.158 iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[1] 999.690 980.965 iice_inst_0.b3_SoW.b9_v_mzCDYXs[0] jtag_interface|b3_PK3_inferred_clock DFN1 D b9_v_mzCDYXs_5[0] 999.590 982.395 =========================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.310 = Required time: 999.690 - Propagation time: 25.102 = Slack (non-critical) : 974.588 Number of logic level(s): 11 Starting point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] / Q Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] DFN1 Q Out 0.364 0.364 - b9_v_mzCDYXs[9] Net - - 6.980 - 106 iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb_7 NOR2B B In - 7.344 - iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb_7 NOR2B Y Out 0.351 7.695 - un10_b11_vfsg_9urxbb_7 Net - - 0.630 - 1 iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb NOR3C C In - 8.325 - iice_inst_0.b3_SoW.b8_vFsG_vuY.un10_b11_vfsg_9urxbb NOR3C Y Out 0.370 8.695 - un10_b11_vfsg_9urxbb Net - - 0.630 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa NOR3A C In - 9.325 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa NOR3A Y Out 0.403 9.728 - b9_v_mzCDYXs_1_sqmuxa Net - - 4.580 - 13 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3 AND2 A In - 14.308 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3 AND2 Y Out 0.293 14.601 - DWACT_ADD_CI_0_TMP[2] Net - - 0.630 - 1 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4 OR3 C In - 15.231 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4 OR3 Y Out 0.416 15.647 - DWACT_ADD_CI_0_g_array_0[0] Net - - 1.060 - 2 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_48 AO1 B In - 16.707 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_48 AO1 Y Out 0.327 17.034 - DWACT_ADD_CI_0_g_array_1[0] Net - - 1.480 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_46 AO1 B In - 18.514 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_46 AO1 Y Out 0.327 18.841 - DWACT_ADD_CI_0_g_array_2[0] Net - - 1.900 - 4 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_50 AO1 B In - 20.741 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_50 AO1 Y Out 0.327 21.067 - DWACT_ADD_CI_0_g_array_3[0] Net - - 1.060 - 2 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_55 AO1 B In - 22.128 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_55 AO1 Y Out 0.327 22.454 - DWACT_ADD_CI_0_g_array_12_3[0] Net - - 0.630 - 1 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_42 XOR2 B In - 23.084 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_42 XOR2 Y Out 0.520 23.604 - I_42_0 Net - - 0.630 - 1 iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[9] OA1A C In - 24.234 - iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[9] OA1A Y Out 0.238 24.472 - b9_v_mzCDYXs_5[9] Net - - 0.630 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] DFN1 D In - 25.102 - ===================================================================================================================== Total path delay (propagation time + setup) of 25.412 is 4.572(18.0%) logic and 20.840(82.0%) route. ==================================== Detailed Report for Clock: jtag_interface|b7_oSD_3vW_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------ comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[0] 0.364 994.618 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[1] 0.364 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[2] 0.364 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[3] 0.364 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[4] 0.364 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[5] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 Q b9_OvyH3_saL[5] 0.364 998.166 ====================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw jtag_interface|b7_oSD_3vW_inferred_clock UJTAG UTDO b6_PLF_Bq 997.000 994.618 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[1] 999.590 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[1] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[2] 999.590 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[2] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[3] 999.590 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[3] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[4] 999.590 998.166 comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[4] jtag_interface|b7_oSD_3vW_inferred_clock DFN1E1 D b9_OvyH3_saL[5] 999.590 998.166 =========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 3.000 = Required time: 997.000 - Propagation time: 2.382 = Slack (non-critical) : 994.618 Number of logic level(s): 1 Starting point: comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] / Q Ending point: comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw / UTDO The start point is clocked by jtag_interface|b7_oSD_3vW_inferred_clock [rising] on pin CLK The end point is clocked by jtag_interface|b7_oSD_3vW_inferred_clock [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------- comm_block_inst.b7_Rcmi_ql.b9_OvyH3_saL[0] DFN1E1 Q Out 0.364 0.364 - b9_OvyH3_saL[0] Net - - 1.060 - 2 comm_block_inst.b7_Rcmi_ql.b3_PLF MX2 A In - 1.424 - comm_block_inst.b7_Rcmi_ql.b3_PLF MX2 Y Out 0.328 1.752 - b6_PLF_Bq Net - - 0.630 - 1 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw UJTAG UTDO In - 2.382 - ============================================================================================================== Total path delay (propagation time + setup) of 5.382 is 3.692(68.6%) logic and 1.690(31.4%) route. ==================================== Detailed Report for Clock: jtag_interface|identify_clk2_no_clk_buffer_needed ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1C1 Q b8_vABZ3qsY 0.364 974.726 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[3] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[2] 0.364 986.326 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[2] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[1] 0.364 986.487 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[1] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[0] 0.364 987.959 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[5] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b12_ORbIwXaEF_bd 0.364 988.530 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[0] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b11_uRrc_WYOFjZ[0] 0.364 989.598 comm_block_inst.b7_Rcmi_ql.b10_dZst39_EF3[4] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E0 Q b13_nvmFL_fx2rbuQ[3] 0.364 989.917 iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[0] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 Q b6_nUT_IF[0] 0.364 998.596 iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[1] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 Q b6_nUT_IF[1] 0.364 998.596 iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b3_nUT[2] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1E1 Q b6_nUT_IF[2] 0.364 998.596 ======================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_2_mzCDYXs[7] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[7] 999.690 974.726 iice_inst_0.b3_SoW.b9_2_mzCDYXs[9] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[9] 999.690 974.726 iice_inst_0.b3_SoW.b9_2_mzCDYXs[6] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[6] 999.690 975.683 iice_inst_0.b3_SoW.b9_2_mzCDYXs[8] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[8] 999.690 975.683 iice_inst_0.b3_SoW.b9_2_mzCDYXs[5] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[5] 999.690 976.113 iice_inst_0.b3_SoW.b9_2_mzCDYXs[4] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[4] 999.690 977.070 iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[7] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b7_nYhI39s_13[7] 999.690 977.783 iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[9] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b7_nYhI39s_13[9] 999.690 977.783 iice_inst_0.b3_SoW.b9_2_mzCDYXs[3] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b9_2_mzCDYXs_5_i[3] 999.690 978.340 iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[6] jtag_interface|identify_clk2_no_clk_buffer_needed DFN1 D b7_nYhI39s_13[6] 999.690 978.740 ===================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.310 = Required time: 999.690 - Propagation time: 24.964 = Slack (non-critical) : 974.726 Number of logic level(s): 13 Starting point: iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY / Q Ending point: iice_inst_0.b3_SoW.b9_2_mzCDYXs[9] / D The start point is clocked by jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK The end point is clocked by jtag_interface|identify_clk2_no_clk_buffer_needed [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ iice_inst_0.b7_12mFLWM.b5_nUTGT.b11_nUTGT_khWqH.b8_vABZ3qsY DFN1E1C1 Q Out 0.364 0.364 - b8_vABZ3qsY Net - - 1.060 - 2 iice_inst_0.b7_12mFLWM.b5_nUTGT.b5_nYhI3.un1_b6_nut_ff_i_o2 OR2B B In - 1.424 - iice_inst_0.b7_12mFLWM.b5_nUTGT.b5_nYhI3.un1_b6_nut_ff_i_o2 OR2B Y Out 0.351 1.775 - N_277 Net - - 1.060 - 2 iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0_a2_0 OR2 B In - 2.835 - iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0_a2_0 OR2 Y Out 0.362 3.197 - N_360 Net - - 1.900 - 4 iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0_a2 NOR2A B In - 5.097 - iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0_a2 NOR2A Y Out 0.232 5.329 - N_380 Net - - 1.060 - 2 iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0 NOR2 B In - 6.389 - iice_inst_0.b7_12mFLWM.b5_nUTGT.b12_voSc3_gmasbb_0 NOR2 Y Out 0.362 6.751 - b8_SoWGfWYY Net - - 5.450 - 22 iice_inst_0.b3_SoW.b8_jAA_KlCO_1_sqmuxa_0_a2 NOR3A A In - 12.201 - iice_inst_0.b3_SoW.b8_jAA_KlCO_1_sqmuxa_0_a2 NOR3A Y Out 0.369 12.570 - b8_jAA_KlCO_1_sqmuxa Net - - 1.480 - 3 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_3 AND2 A In - 14.050 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_3 AND2 Y Out 0.293 14.342 - DWACT_ADD_CI_0_TMP_0[2] Net - - 0.630 - 1 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_4 OR3 C In - 14.973 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_4 OR3 Y Out 0.416 15.389 - DWACT_ADD_CI_0_g_array_0_0[0] Net - - 1.060 - 2 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_48 AO1 B In - 16.448 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_48 AO1 Y Out 0.327 16.775 - DWACT_ADD_CI_0_g_array_1_0[0] Net - - 1.480 - 3 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_46 AO1 B In - 18.255 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_46 AO1 Y Out 0.327 18.582 - DWACT_ADD_CI_0_g_array_2_0[0] Net - - 1.900 - 4 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_50 AO1 B In - 20.482 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_50 AO1 Y Out 0.327 20.809 - DWACT_ADD_CI_0_g_array_3_0[0] Net - - 1.060 - 2 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_55 AO1 B In - 21.869 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_55 AO1 Y Out 0.327 22.196 - DWACT_ADD_CI_0_g_array_12_3_0[0] Net - - 0.630 - 1 iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_42 XOR2 B In - 22.826 - iice_inst_0.b3_SoW.un1_b9_2_mzCDYXs.I_42 XOR2 Y Out 0.520 23.346 - I_42_1 Net - - 0.630 - 1 iice_inst_0.b3_SoW.b8_2FsG_vuY.b9_2_mzCDYXs_5_i[9] NOR3B B In - 23.976 - iice_inst_0.b3_SoW.b8_2FsG_vuY.b9_2_mzCDYXs_5_i[9] NOR3B Y Out 0.358 24.334 - b9_2_mzCDYXs_5_i[9] Net - - 0.630 - 1 iice_inst_0.b3_SoW.b9_2_mzCDYXs[9] DFN1 D In - 24.964 - ============================================================================================================================== Total path delay (propagation time + setup) of 25.274 is 5.244(20.7%) logic and 20.030(79.3%) route. ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UIREG3 b6_uS_MrX[2] 3.000 958.379 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UIREG5 b6_uS_MrX[4] 3.000 958.393 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UIREG4 b6_uS_MrX[3] 3.000 958.519 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UIREG2 b6_uS_MrX[1] 3.000 959.412 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UIREG6 b3_1Um 3.000 959.531 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UIREG1 b6_uS_MrX[0] 3.000 960.364 comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw System UJTAG UDRCAP b7_nFG0rDY 3.000 961.646 iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[2] System DFN1 Q b7_nYhI39s[2] 0.364 968.410 iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[8] System DFN1 Q b7_nYhI39s[8] 0.364 968.467 iice_inst_0.b7_12mFLWM.b5_nUTGT.b7_nYhI39s[4] System DFN1 Q b7_nYhI39s[4] 0.364 968.479 ========================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- iice_inst_0.b3_SoW.b9_v_mzCDYXs[7] System DFN1 D b9_v_mzCDYXs_5[7] 999.690 958.379 iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] System DFN1 D b9_v_mzCDYXs_5[9] 999.690 958.379 iice_inst_0.b3_SoW.b9_v_mzCDYXs[6] System DFN1 D b9_v_mzCDYXs_5[6] 999.690 959.336 iice_inst_0.b3_SoW.b9_v_mzCDYXs[8] System DFN1 D b9_v_mzCDYXs_5[8] 999.690 959.336 iice_inst_0.b3_SoW.b9_v_mzCDYXs[5] System DFN1 D b9_v_mzCDYXs_5[5] 999.690 959.766 iice_inst_0.b3_SoW.b9_v_mzCDYXs[4] System DFN1 D b9_v_mzCDYXs_5[4] 999.690 960.723 iice_inst_0.b3_SoW.b9_v_mzCDYXs[3] System DFN1 D b9_v_mzCDYXs_5[3] 999.690 961.993 iice_inst_0.b3_SoW.b9_v_mzCDYXs[2] System DFN1 D b9_v_mzCDYXs_5[2] 999.690 962.949 iice_inst_0.b3_SoW.b9_v_mzCDYXs[1] System DFN1 D b9_v_mzCDYXs_5[1] 999.690 964.756 iice_inst_0.b3_SoW.b9_v_mzCDYXs[0] System DFN1 D b9_v_mzCDYXs_5[0] 999.590 966.186 ================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.310 = Required time: 999.690 - Propagation time: 41.311 = Slack (non-critical) : 958.379 Number of logic level(s): 14 Starting point: comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw / UIREG3 Ending point: iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] / D The start point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] The end point is clocked by jtag_interface|b3_PK3_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ comm_block_inst.jtag_block.jtagi.b9_Rcmi_KsDw UJTAG UIREG3 Out 0.000 3.000 - b6_uS_MrX[2] Net - - 0.630 - 1 comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_2_1 OR3 C In - 3.630 - comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_2_1 OR3 Y Out 0.416 4.046 - b9_nv_cLqgOF_2_1 Net - - 1.060 - 2 comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_0 OR3A B In - 5.106 - comm_block_inst.jtag_block.jtagi.b9_nv_cLqgOF_0 OR3A Y Out 0.403 5.509 - b9_nv_cLqgOF_0 Net - - 1.900 - 4 comm_block_inst.jtag_block.jtagi.b10_nv_ywKMm9X NOR3B C In - 7.409 - comm_block_inst.jtag_block.jtagi.b10_nv_ywKMm9X NOR3B Y Out 0.276 7.685 - b10_nv_ywKMm9X Net - - 6.180 - 33 I_75 CLKINT A In - 13.865 - I_75 CLKINT Y Out 0.100 13.965 - comm2iice_link_iice_0_a_0[7] Net - - 4.580 - 38 iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b6_yor0PD_0_sqmuxa OR2B A In - 18.545 - iice_inst_0.b3_SoW.b11_OFWNT9_X1eH.b6_yor0PD_0_sqmuxa OR2B Y Out 0.293 18.838 - b14_voSc3_sr2kFHQz Net - - 6.730 - 55 iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa NOR3A A In - 25.568 - iice_inst_0.b3_SoW.b9_v_mzCDYXs_1_sqmuxa NOR3A Y Out 0.369 25.937 - b9_v_mzCDYXs_1_sqmuxa Net - - 4.580 - 13 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3 AND2 A In - 30.517 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_3 AND2 Y Out 0.293 30.810 - DWACT_ADD_CI_0_TMP[2] Net - - 0.630 - 1 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4 OR3 C In - 31.440 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_4 OR3 Y Out 0.416 31.856 - DWACT_ADD_CI_0_g_array_0[0] Net - - 1.060 - 2 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_48 AO1 B In - 32.916 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_48 AO1 Y Out 0.327 33.243 - DWACT_ADD_CI_0_g_array_1[0] Net - - 1.480 - 3 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_46 AO1 B In - 34.723 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_46 AO1 Y Out 0.327 35.050 - DWACT_ADD_CI_0_g_array_2[0] Net - - 1.900 - 4 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_50 AO1 B In - 36.950 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_50 AO1 Y Out 0.327 37.276 - DWACT_ADD_CI_0_g_array_3[0] Net - - 1.060 - 2 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_55 AO1 B In - 38.336 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_55 AO1 Y Out 0.327 38.663 - DWACT_ADD_CI_0_g_array_12_3[0] Net - - 0.630 - 1 iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_42 XOR2 B In - 39.293 - iice_inst_0.b3_SoW.un1_b9_v_mzCDYXs.I_42 XOR2 Y Out 0.520 39.813 - I_42_0 Net - - 0.630 - 1 iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[9] OA1A C In - 40.443 - iice_inst_0.b3_SoW.b8_vFsG_vuY.b9_v_mzCDYXs_5[9] OA1A Y Out 0.238 40.681 - b9_v_mzCDYXs_5[9] Net - - 0.630 - 1 iice_inst_0.b3_SoW.b9_v_mzCDYXs[9] DFN1 D In - 41.311 - ======================================================================================================================== Total path delay (propagation time + setup) of 41.621 is 4.941(11.9%) logic and 33.680(80.9%) route. ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Report for cell config_top.rtl Cell usage: cell count area count*area DFN1 287 1.0 287.0 MX2C 201 1.0 201.0 MX2 185 1.0 185.0 DFN1E1 144 1.0 144.0 XOR2 129 1.0 129.0 NOR2B 118 1.0 118.0 VCC 84 0.0 0.0 GND 84 0.0 0.0 DFN1C1 79 1.0 79.0 AO1 79 1.0 79.0 OR2B 65 1.0 65.0 NOR3C 64 1.0 64.0 DFN1E1C1 61 1.0 61.0 NOR2 61 1.0 61.0 AND2 60 1.0 60.0 XNOR2 51 1.0 51.0 NOR2A 49 1.0 49.0 AOI1B 44 1.0 44.0 DFN1E0 42 1.0 42.0 ZOR3I 33 1.0 33.0 NOR3B 31 1.0 31.0 OR2 31 1.0 31.0 OAI1 30 1.0 30.0 NOR3A 27 1.0 27.0 NOR3 25 1.0 25.0 OR3B 24 1.0 24.0 AX1B 23 1.0 23.0 AND3 22 1.0 22.0 OR2A 21 1.0 21.0 OR3A 20 1.0 20.0 OR3 12 1.0 12.0 DFN1P1 12 1.0 12.0 RAM512X18 12 0.0 0.0 OA1A 11 1.0 11.0 INV 11 1.0 11.0 XO1 10 1.0 10.0 OR3C 10 1.0 10.0 AOI1 10 1.0 10.0 DFN0C1 8 1.0 8.0 OA1B 8 1.0 8.0 DFN1E1P1 8 1.0 8.0 AX1 7 1.0 7.0 MAJ3 6 1.0 6.0 AO1B 6 1.0 6.0 BUFF 5 1.0 5.0 OA1 5 1.0 5.0 AO1A 5 1.0 5.0 AO1C 4 1.0 4.0 AO1D 4 1.0 4.0 XO1A 4 1.0 4.0 OA1C 3 1.0 3.0 MX2A 3 1.0 3.0 AX1C 3 1.0 3.0 CLKBUF 2 0.0 0.0 NVM 2 0.0 0.0 XA1A 2 1.0 2.0 CLKINT 2 0.0 0.0 INBUF 2 0.0 0.0 PLL 1 0.0 0.0 XA1C 1 1.0 1.0 BIBUF 1 0.0 0.0 XNOR3 1 1.0 1.0 RCOSC 1 0.0 0.0 UJTAG 1 0.0 0.0 RAM4K9 1 0.0 0.0 AO13 1 1.0 1.0 MX2B 1 1.0 1.0 AX1E 1 1.0 1.0 MIN3 1 1.0 1.0 MIN3XI 1 1.0 1.0 ----- ---------- TOTAL 2363 2170.0 Mapper successful! Process took 0h:00m:13s realtime, 0h:00m:12s cputime # Thu Feb 08 18:47:30 2007 ###########################################################]