#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: T:\releases\production\Libero\Libero_90\PC_9_0_0_19_SPB\Synopsys\synplify_D200912A #OS: Windows XP 5.1 #Hostname: VXP-PINJALAS #Implementation: synthesis #Fri Sep 03 19:44:55 2010 $ Start of Compile #Fri Sep 03 19:44:55 2010 Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"T:\releases\production\Libero\Libero_90\PC_9_0_0_19_SPB\Synopsys\synplify_D200912A\lib\proasic\igloo.v" @I::"C:\Actelprj\Libero_tutorial\smartgen\Counter2\Counter2.v" @I::"C:\Actelprj\Libero_tutorial\smartgen\CLKGEN\CLKGEN.v" @I::"C:\Actelprj\Libero_tutorial\smartgen\Counter1\Counter1.v" @I::"C:\Actelprj\Libero_tutorial\component\work\Top\Top.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module Top @N:CG364 : igloo.v(2) | Synthesizing module AND2 @N:CG364 : igloo.v(977) | Synthesizing module DFN1E1C0 @N:CG364 : igloo.v(1283) | Synthesizing module INV @N:CG364 : igloo.v(929) | Synthesizing module DFN1C0 @N:CG364 : igloo.v(1929) | Synthesizing module XOR2 @N:CG364 : igloo.v(20) | Synthesizing module AND3 @N:CG364 : Counter2.v(5) | Synthesizing module Counter2 @W:CL168 : Counter2.v(26) | Pruning instance U_AND3_0_1_2 - not in use ... @W:CL168 : Counter2.v(20) | Pruning instance U_AND2_0_1 - not in use ... @N:CG364 : igloo.v(1864) | Synthesizing module VCC @N:CG364 : igloo.v(1163) | Synthesizing module GND @N:CG364 : igloo.v(2447) | Synthesizing module PLL @N:CG364 : igloo.v(276) | Synthesizing module PLLINT @N:CG364 : CLKGEN.v(5) | Synthesizing module CLKGEN @N:CG364 : Counter1.v(5) | Synthesizing module Counter1 @W:CL168 : Counter1.v(98) | Pruning instance U_AND3_15_16_17 - not in use ... @W:CL168 : Counter1.v(97) | Pruning instance U_AND2_3_4 - not in use ... @W:CL168 : Counter1.v(92) | Pruning instance U_U_AND3_9_to_17 - not in use ... @W:CL168 : Counter1.v(30) | Pruning instance U_AND2_9_10 - not in use ... @W:CL168 : Counter1.v(25) | Pruning instance U_AND2_0_1 - not in use ... @N:CG364 : igloo.v(2762) | Synthesizing module INBUF_FF @N:CG364 : Top.v(5) | Synthesizing module Top @W:CL168 : Top.v(24) | Pruning instance GND - not in use ... @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Sep 03 19:44:57 2010 ###########################################################] Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version D-2009.12A @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Automatic dissolve at startup in view:work.Top(verilog) of Counter1_0(Counter1) Automatic dissolve at startup in view:work.Top(verilog) of CLKGEN_0(CLKGEN) Automatic dissolve at startup in view:work.Top(verilog) of Counter2_0(Counter2) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) @N:FP130 : | Promoting Net Counter1_0_Q17to17 on CLKINT Counter1_0.Counter1_0_Q17to17_inferred_clock Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Writing Analyst data base C:\Actelprj\Libero_tutorial\synthesis\Top.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) Writing EDIF Netlist and constraint files D-2009.12A Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 56MB) @W:MT420 : | Found inferred clock Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:CLKGEN_0_GLA" @W:MT420 : | Found inferred clock Top|Counter1_0.Counter1_0_Q17to17_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:Counter1_0_Q17to17" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Sep 03 19:45:08 2010 # Top view: Top Library name: IGLOO_V2 Operating conditions: COMWCSTD ( T = 70.0, V = 1.14, P = 3.70, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: igloo Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -6.918 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------- Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock 100.0 MHz 59.1 MHz 10.000 16.918 -6.918 inferred Inferred_clkgroup_1 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock 100.0 MHz 91.4 MHz 10.000 10.942 -0.942 inferred Inferred_clkgroup_0 ======================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Top|Counter1_0.Counter1_0_Q17to17_inferred_clock Top|Counter1_0.Counter1_0_Q17to17_inferred_clock | 10.000 -0.942 | No paths - | No paths - | No paths - Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock | 10.000 -6.918 | No paths - | No paths - | No paths - =========================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------- Counter1_0.DFN1C0_NU_0 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1C0 Q DFN1C0_NU_0 1.771 -6.918 Counter1_0.DFN1E1C0_NU_7 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_7 1.771 -6.141 Counter1_0.DFN1E1C0_NU_3 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_3 1.771 -5.899 Counter1_0.DFN1E1C0_NU_13 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_13 1.771 -5.870 Counter1_0.DFN1E1C0_NU_9 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_9 1.771 -5.782 Counter1_0.DFN1E1C0_NU_1 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_1 1.771 -5.586 Counter1_0.DFN1C0_NU_2 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1C0 Q DFN1C0_NU_2 1.771 -4.918 Counter1_0.DFN1E1C0_NU_4 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_4 1.771 -4.567 Counter1_0.DFN1E1C0_NU_10 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 Q DFN1E1C0_NU_10 1.771 -4.450 Counter1_0.DFN1C0_NU_6 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1C0 Q DFN1C0_NU_6 1.771 -4.057 ===================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- Counter1_0.DFN1E1C0_NU_16 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 D XOR2_12_Y 8.789 -6.918 Counter1_0.DFN1E1C0_NU_17 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 D XOR2_8_Y 8.789 -6.918 Counter1_0.DFN1E1C0_NU_9 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1E1C0_NU_10 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1E1C0_NU_11 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1E1C0_NU_12 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1E1C0_NU_13 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1E1C0_NU_14 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1E1C0_NU_15 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1E1C0 E NU_0_to_8 8.538 -6.680 Counter1_0.DFN1C0_NU_6 Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock DFN1C0 D XOR2_10_Y 8.705 -4.429 ================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.211 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.789 - Propagation time: 15.707 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -6.918 Number of logic level(s): 3 Starting point: Counter1_0.DFN1C0_NU_0 / Q Ending point: Counter1_0.DFN1E1C0_NU_16 / D The start point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK The end point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- Counter1_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - DFN1C0_NU_0 Net - - 2.844 - 4 Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C C In - 4.615 - Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C Y Out 1.541 6.156 - NU_0_1_2 Net - - 3.938 - 8 Counter1_0.DFN1E1C0_NU_11_RNIPJ4U OR2B B In - 10.094 - Counter1_0.DFN1E1C0_NU_11_RNIPJ4U OR2B Y Out 1.508 11.602 - G_10_0_0_o2_6 Net - - 0.927 - 2 Counter1_0.DFN1E1C0_NU_16_RNO AX1B B In - 12.529 - Counter1_0.DFN1E1C0_NU_16_RNO AX1B Y Out 2.406 14.934 - XOR2_12_Y Net - - 0.773 - 1 Counter1_0.DFN1E1C0_NU_16 DFN1E1C0 D In - 15.707 - ==================================================================================================== Total path delay (propagation time + setup) of 16.918 is 8.436(49.9%) logic and 8.482(50.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 1.211 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.789 - Propagation time: 15.707 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -6.918 Number of logic level(s): 3 Starting point: Counter1_0.DFN1C0_NU_0 / Q Ending point: Counter1_0.DFN1E1C0_NU_17 / D The start point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK The end point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- Counter1_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - DFN1C0_NU_0 Net - - 2.844 - 4 Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C C In - 4.615 - Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C Y Out 1.541 6.156 - NU_0_1_2 Net - - 3.938 - 8 Counter1_0.DFN1E1C0_NU_11_RNIPJ4U OR2B B In - 10.094 - Counter1_0.DFN1E1C0_NU_11_RNIPJ4U OR2B Y Out 1.508 11.602 - G_10_0_0_o2_6 Net - - 0.927 - 2 Counter1_0.DFN1E1C0_NU_17_RNO AX1B B In - 12.529 - Counter1_0.DFN1E1C0_NU_17_RNO AX1B Y Out 2.406 14.934 - XOR2_8_Y Net - - 0.773 - 1 Counter1_0.DFN1E1C0_NU_17 DFN1E1C0 D In - 15.707 - ==================================================================================================== Total path delay (propagation time + setup) of 16.918 is 8.436(49.9%) logic and 8.482(50.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 1.462 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.538 - Propagation time: 15.218 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -6.680 Number of logic level(s): 2 Starting point: Counter1_0.DFN1C0_NU_0 / Q Ending point: Counter1_0.DFN1E1C0_NU_9 / E The start point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK The end point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- Counter1_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - DFN1C0_NU_0 Net - - 2.844 - 4 Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C C In - 4.615 - Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C Y Out 1.541 6.156 - NU_0_1_2 Net - - 3.938 - 8 Counter1_0.DFN1E1C0_NU_8_RNIF2GR1 NOR3B B In - 10.094 - Counter1_0.DFN1E1C0_NU_8_RNIF2GR1 NOR3B Y Out 1.458 11.552 - NU_0_to_8 Net - - 3.667 - 7 Counter1_0.DFN1E1C0_NU_9 DFN1E1C0 E In - 15.218 - ==================================================================================================== Total path delay (propagation time + setup) of 16.680 is 6.231(37.4%) logic and 10.449(62.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 1.462 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.538 - Propagation time: 15.218 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -6.680 Number of logic level(s): 2 Starting point: Counter1_0.DFN1C0_NU_0 / Q Ending point: Counter1_0.DFN1E1C0_NU_15 / E The start point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK The end point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- Counter1_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - DFN1C0_NU_0 Net - - 2.844 - 4 Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C C In - 4.615 - Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C Y Out 1.541 6.156 - NU_0_1_2 Net - - 3.938 - 8 Counter1_0.DFN1E1C0_NU_8_RNIF2GR1 NOR3B B In - 10.094 - Counter1_0.DFN1E1C0_NU_8_RNIF2GR1 NOR3B Y Out 1.458 11.552 - NU_0_to_8 Net - - 3.667 - 7 Counter1_0.DFN1E1C0_NU_15 DFN1E1C0 E In - 15.218 - ==================================================================================================== Total path delay (propagation time + setup) of 16.680 is 6.231(37.4%) logic and 10.449(62.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 1.462 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.538 - Propagation time: 15.218 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -6.680 Number of logic level(s): 2 Starting point: Counter1_0.DFN1C0_NU_0 / Q Ending point: Counter1_0.DFN1E1C0_NU_13 / E The start point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK The end point is clocked by Top|CLKGEN_0.CLKGEN_0_GLA_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- Counter1_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - DFN1C0_NU_0 Net - - 2.844 - 4 Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C C In - 4.615 - Counter1_0.DFN1C0_NU_2_RNI0T2K NOR3C Y Out 1.541 6.156 - NU_0_1_2 Net - - 3.938 - 8 Counter1_0.DFN1E1C0_NU_8_RNIF2GR1 NOR3B B In - 10.094 - Counter1_0.DFN1E1C0_NU_8_RNIF2GR1 NOR3B Y Out 1.458 11.552 - NU_0_to_8 Net - - 3.667 - 7 Counter1_0.DFN1E1C0_NU_13 DFN1E1C0 E In - 15.218 - ==================================================================================================== Total path delay (propagation time + setup) of 16.680 is 6.231(37.4%) logic and 10.449(62.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Top|Counter1_0.Counter1_0_Q17to17_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------ Counter2_0.DFN1C0_NU_0 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1C0 Q Q_c[0] 1.771 -0.942 Counter2_0.DFN1E1C0_NU_1 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1E1C0 Q Q_c[1] 1.771 -0.307 Counter2_0.DFN1C0_NU_2 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1C0 Q Q_c[2] 1.771 4.061 ==================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------- Counter2_0.DFN1C0_NU_2 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1C0 D XOR2_0_Y 8.705 -0.942 Counter2_0.DFN1C0_NU_0 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1C0 D INV_1_Y 8.705 2.099 Counter2_0.DFN1E1C0_NU_1 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1E1C0 D INV_0_Y 8.705 3.005 Counter2_0.DFN1E1C0_NU_1 Top|Counter1_0.Counter1_0_Q17to17_inferred_clock DFN1E1C0 E Q_c[0] 8.538 3.924 ======================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 9.647 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.942 Number of logic level(s): 2 Starting point: Counter2_0.DFN1C0_NU_0 / Q Ending point: Counter2_0.DFN1C0_NU_2 / D The start point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK The end point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- Counter2_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - Q_c[0] Net - - 2.844 - 4 Counter2_0.AND2_0 AND2 A In - 4.615 - Counter2_0.AND2_0 AND2 Y Out 1.236 5.851 - AND2_0_Y Net - - 0.773 - 1 Counter2_0.XOR2_0 XOR2 B In - 6.624 - Counter2_0.XOR2_0 XOR2 Y Out 2.251 8.875 - XOR2_0_Y Net - - 0.773 - 1 Counter2_0.DFN1C0_NU_2 DFN1C0 D In - 9.647 - ======================================================================================= Total path delay (propagation time + setup) of 10.942 is 6.553(59.9%) logic and 4.389(40.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 9.012 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.307 Number of logic level(s): 2 Starting point: Counter2_0.DFN1E1C0_NU_1 / Q Ending point: Counter2_0.DFN1C0_NU_2 / D The start point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK The end point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- Counter2_0.DFN1E1C0_NU_1 DFN1E1C0 Q Out 1.771 1.771 - Q_c[1] Net - - 1.938 - 3 Counter2_0.AND2_0 AND2 B In - 3.708 - Counter2_0.AND2_0 AND2 Y Out 1.508 5.216 - AND2_0_Y Net - - 0.773 - 1 Counter2_0.XOR2_0 XOR2 B In - 5.989 - Counter2_0.XOR2_0 XOR2 Y Out 2.251 8.240 - XOR2_0_Y Net - - 0.773 - 1 Counter2_0.DFN1C0_NU_2 DFN1C0 D In - 9.012 - =========================================================================================== Total path delay (propagation time + setup) of 10.307 is 6.824(66.2%) logic and 3.483(33.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 6.607 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 2.099 Number of logic level(s): 1 Starting point: Counter2_0.DFN1C0_NU_0 / Q Ending point: Counter2_0.DFN1C0_NU_0 / D The start point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK The end point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------- Counter2_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - Q_c[0] Net - - 2.844 - 4 Counter2_0.INV_1 INV A In - 4.615 - Counter2_0.INV_1 INV Y Out 1.219 5.834 - INV_1_Y Net - - 0.773 - 1 Counter2_0.DFN1C0_NU_0 DFN1C0 D In - 6.607 - ======================================================================================= Total path delay (propagation time + setup) of 7.901 is 4.285(54.2%) logic and 3.617(45.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 1.295 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.705 - Propagation time: 5.700 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.005 Number of logic level(s): 1 Starting point: Counter2_0.DFN1E1C0_NU_1 / Q Ending point: Counter2_0.DFN1E1C0_NU_1 / D The start point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK The end point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- Counter2_0.DFN1E1C0_NU_1 DFN1E1C0 Q Out 1.771 1.771 - Q_c[1] Net - - 1.938 - 3 Counter2_0.INV_0 INV A In - 3.708 - Counter2_0.INV_0 INV Y Out 1.219 4.928 - INV_0_Y Net - - 0.773 - 1 Counter2_0.DFN1E1C0_NU_1 DFN1E1C0 D In - 5.700 - =========================================================================================== Total path delay (propagation time + setup) of 6.995 is 4.285(61.3%) logic and 2.710(38.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 1.462 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.538 - Propagation time: 4.615 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.923 Number of logic level(s): 0 Starting point: Counter2_0.DFN1C0_NU_0 / Q Ending point: Counter2_0.DFN1E1C0_NU_1 / E The start point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK The end point is clocked by Top|Counter1_0.Counter1_0_Q17to17_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- Counter2_0.DFN1C0_NU_0 DFN1C0 Q Out 1.771 1.771 - Q_c[0] Net - - 2.844 - 4 Counter2_0.DFN1E1C0_NU_1 DFN1E1C0 E In - 4.615 - =========================================================================================== Total path delay (propagation time + setup) of 6.077 is 3.232(53.2%) logic and 2.844(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: AGLN250V2Z_VQFP100_Std Report for cell Top.verilog Core Cell usage: cell count area count*area AND2 7 1.0 7.0 AX1 2 1.0 2.0 AX1B 2 1.0 2.0 AX1C 4 1.0 4.0 CLKINT 1 0.0 0.0 GND 4 0.0 0.0 INV 6 1.0 6.0 NOR3B 1 1.0 1.0 NOR3C 3 1.0 3.0 OR2B 4 1.0 4.0 OR3A 1 1.0 1.0 OR3B 1 1.0 1.0 OR3C 2 1.0 2.0 PLL 1 0.0 0.0 PLLINT 1 0.0 0.0 VCC 4 0.0 0.0 XOR2 7 1.0 7.0 DFN1C0 5 1.0 5.0 DFN1E1C0 16 1.0 16.0 ----- ---------- TOTAL 72 61.0 IO Cell usage: cell count INBUF 2 INBUF_FF 1 OUTBUF 3 ----- TOTAL 6 Core Cells : 61 of 6144 (1%) IO Cells : 6 of 68 (9%) RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:04s realtime, 0h:00m:01s cputime # Fri Sep 03 19:45:09 2010 ###########################################################]