#Build: Synplify Pro 9.4A1, Build 169R, Jun 11 2008 #install: D:\actel_sw\Libero84\Libero_v8.4\Synplify\synplify_94A1 #OS: Windows XP 5.1 #Hostname: WXPL-ALEXANDER #Implementation: synthesis #Sat Sep 13 16:07:53 2008 $ Start of Compile #Sat Sep 13 16:07:53 2008 Synplicity VHDL Compiler, version 1.0, Build 061R, built Jun 30 2008 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns Top entity isn't set yet! VHDL syntax check successful! Options changed - recompiling @N:CD630 : Top.vhd(17) | Synthesizing work.top.rtl @N:CD364 : Top.vhd(173) | Removed redundant assignment @N:CD364 : Top.vhd(201) | Removed redundant assignment @N:CD630 : NVM_sysm.vhd(8) | Synthesizing work.nvm_sysm.def_arch @N:CD630 : fusion.vhd(4477) | Synthesizing fusion.nvm.syn_black_box Post processing for fusion.nvm.syn_black_box @N:CD630 : fusion.vhd(3019) | Synthesizing fusion.vcc.syn_black_box Post processing for fusion.vcc.syn_black_box @N:CD630 : fusion.vhd(1899) | Synthesizing fusion.gnd.syn_black_box Post processing for fusion.gnd.syn_black_box @N:CD630 : NVM_sysm_init_wrapper.vhd(127) | Synthesizing work.nvm_sysm_init_wrapper.def_arch @N:CD630 : initcfg.vhd(585) | Synthesizing work.initcfg.behavior @N:CD630 : initcfg.vhd(10) | Synthesizing work.grwzcnqmqzm.mjtkskcsjhk @N:CD630 : initcfg_xf.vhd(37) | Synthesizing work.initcfg_xf.behavior @N:CD630 : initcfg_xf.vhd(10) | Synthesizing work.jhmkpjjmdkx.bmnqpbgpmvq Post processing for work.jhmkpjjmdkx.bmnqpbgpmvq Post processing for work.initcfg_xf.behavior @N:CD630 : initcfg_xe.vhd(27) | Synthesizing work.initcfg_xe.behavior @N:CD630 : initcfg_xe.vhd(10) | Synthesizing work.gpbdjfttbjd.zsftcmnmkdb Post processing for work.gpbdjfttbjd.zsftcmnmkdb Post processing for work.initcfg_xe.behavior @N:CD630 : initcfg_xd.vhd(56) | Synthesizing work.initcfg_xd.behavior @N:CD630 : initcfg_xd.vhd(10) | Synthesizing work.dxwqxgdccxc.cmvhvtvbzkh Post processing for work.dxwqxgdccxc.cmvhvtvbzkh Post processing for work.initcfg_xd.behavior @N:CD630 : initcfg_xc.vhd(155) | Synthesizing work.initcfg_xc.behavior @N:CD630 : initcfg_xc.vhd(10) | Synthesizing work.ffppvfwnggt.zgctkkxfnjk Post processing for work.ffppvfwnggt.zgctkkxfnjk Post processing for work.initcfg_xc.behavior @N:CD630 : initcfg_xb.vhd(70) | Synthesizing work.initcfg_xb.behavior @N:CD630 : initcfg_xb.vhd(11) | Synthesizing work.wbsfnwwctpn.mmwvfpfbppr @N:CD231 : initcfg_xb.vhd(23) | Using onehot encoding for type cjhswcdjptj (cqppqjpknwn="100000000") Post processing for work.wbsfnwwctpn.mmwvfpfbppr Post processing for work.initcfg_xb.behavior @N:CD630 : initcfg_xa.vhd(57) | Synthesizing work.initcfg_xa.behavior @N:CD630 : initcfg_xa.vhd(11) | Synthesizing work.stnpfdkggvx.zkzbcmxmrjf @N:CD231 : initcfg_xa.vhd(21) | Using onehot encoding for type bfjbqwgdgfk (tvzdqnwfvfh="10000000") Post processing for work.stnpfdkggvx.zkzbcmxmrjf Post processing for work.initcfg_xa.behavior Post processing for work.grwzcnqmqzm.mjtkskcsjhk Post processing for work.initcfg.behavior Post processing for work.nvm_sysm_init_wrapper.def_arch Post processing for work.nvm_sysm.def_arch @W:CL168 : NVM_sysm.vhd(375) | Pruning instance VCC_power_inst1 - not in use ... @N:CD630 : Analog_proc1.vhd(8) | Synthesizing work.analog_proc1.def_arch @N:CD630 : fusion.vhd(4037) | Synthesizing fusion.ab.syn_black_box Post processing for fusion.ab.syn_black_box @N:CD630 : fusion.vhd(1332) | Synthesizing fusion.dfn0c0.syn_black_box Post processing for fusion.dfn0c0.syn_black_box @N:CD630 : fusion.vhd(2389) | Synthesizing fusion.or2a.syn_black_box Post processing for fusion.or2a.syn_black_box @N:CD630 : fusion.vhd(1912) | Synthesizing fusion.inbuf_a.syn_black_box Post processing for fusion.inbuf_a.syn_black_box @N:CD630 : fusion.vhd(1460) | Synthesizing fusion.dfn0p0.syn_black_box Post processing for fusion.dfn0p0.syn_black_box @N:CD630 : Analog_proc1_assc_wrapper.vhd(115) | Synthesizing work.analog_proc1_assc_wrapper.def_arch @N:CD630 : assc.vhd(347) | Synthesizing work.assc.behv @N:CD630 : assc.vhd(10) | Synthesizing work.fmvgpwbdcxs.twzmfpzvmcf @N:CD231 : assc.vhd(79) | Using onehot encoding for type hnjbjrqsbmg (mdqdmchqsjk="1000000000000000") Post processing for work.fmvgpwbdcxs.twzmfpzvmcf @W:CL169 : assc.vhd(275) | Pruning Register sxqvnxkkjsh(9 downto 0) @W:CL169 : assc.vhd(275) | Pruning Register njsdcspkqtt @W:CL169 : assc.vhd(275) | Pruning Register jzwhhbvmkpk @W:CL169 : assc.vhd(275) | Pruning Register kzdxfwqwvrt @W:CL170 : assc.vhd(291) | Pruning bit <9> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <8> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <7> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <6> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <5> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <4> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <3> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <2> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <1> of bwngcbddzsh(10 downto 0) - not in use ... @W:CL170 : assc.vhd(291) | Pruning bit <0> of bwngcbddzsh(10 downto 0) - not in use ... Post processing for work.assc.behv Post processing for work.analog_proc1_assc_wrapper.def_arch @N:CD630 : fusion.vhd(2381) | Synthesizing fusion.or2.syn_black_box Post processing for fusion.or2.syn_black_box @N:CD630 : Analog_proc1_assc_ram.vhd(8) | Synthesizing work.analog_proc1_assc_ram.def_arch @N:CD630 : fusion.vhd(3182) | Synthesizing fusion.ram4k9.syn_black_box Post processing for fusion.ram4k9.syn_black_box Post processing for work.analog_proc1_assc_ram.def_arch @N:CD630 : Analog_proc1_abdelay_counter.vhd(8) | Synthesizing work.analog_proc1_abdelay_counter.def_arch @N:CD630 : fusion.vhd(37) | Synthesizing fusion.and3.syn_black_box Post processing for fusion.and3.syn_black_box @N:CD630 : fusion.vhd(2117) | Synthesizing fusion.inv.syn_black_box Post processing for fusion.inv.syn_black_box @N:CD630 : fusion.vhd(13) | Synthesizing fusion.and2.syn_black_box Post processing for fusion.and2.syn_black_box @N:CD630 : fusion.vhd(3114) | Synthesizing fusion.xor2.syn_black_box Post processing for fusion.xor2.syn_black_box @N:CD630 : fusion.vhd(1584) | Synthesizing fusion.dfn1e1c0.syn_black_box Post processing for fusion.dfn1e1c0.syn_black_box @N:CD630 : fusion.vhd(1500) | Synthesizing fusion.dfn1c0.syn_black_box Post processing for fusion.dfn1c0.syn_black_box Post processing for work.analog_proc1_abdelay_counter.def_arch @W:CL168 : Analog_proc1_abdelay_counter.vhd(381) | Pruning instance U_AND2_3_4 - not in use ... @W:CL168 : Analog_proc1_abdelay_counter.vhd(234) | Pruning instance U_U_AND3_18_to_24 - not in use ... @W:CL168 : Analog_proc1_abdelay_counter.vhd(161) | Pruning instance U_AND2_9_10 - not in use ... @W:CL168 : Analog_proc1_abdelay_counter.vhd(131) | Pruning instance U_AND2_0_1 - not in use ... @N:CD630 : fusion.vhd(21) | Synthesizing fusion.and2a.syn_black_box Post processing for fusion.and2a.syn_black_box Post processing for work.analog_proc1.def_arch @W:CL168 : Analog_proc1.vhd(762) | Pruning instance VCC_power_inst1 - not in use ... Post processing for work.top.rtl @W:CL240 : Top.vhd(24) | RESULT_TEMP is not assigned a value (floating) - a simulation mismatch is possible @W:CL240 : Top.vhd(23) | RESULT_AV5V is not assigned a value (floating) - a simulation mismatch is possible @N:CL201 : assc.vhd(268) | Trying to extract state machine for register jzzdfrmzwdj Extracted state machine for register jzzdfrmzwdj State machine has 16 reachable states with original encodings of: 0000000000000001 0000000000000010 0000000000000100 0000000000001000 0000000000010000 0000000000100000 0000000001000000 0000000010000000 0000000100000000 0000001000000000 0000010000000000 0000100000000000 0001000000000000 0010000000000000 0100000000000000 1000000000000000 @W:CL159 : assc.vhd(21) | Input vhqjcrxqhqk is unused @W:CL159 : assc.vhd(21) | Input vhsprbpmpnr is unused @N:CL201 : initcfg_xa.vhd(41) | Trying to extract state machine for register mwtvnzdkmwm Extracted state machine for register mwtvnzdkmwm State machine has 8 reachable states with original encodings of: 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 @N:CL201 : initcfg_xb.vhd(47) | Trying to extract state machine for register crpwsdfhcqq Extracted state machine for register crpwsdfhcqq State machine has 9 reachable states with original encodings of: 000000001 000000010 000000100 000001000 000010000 000100000 001000000 010000000 100000000 @W:CL171 : Top.vhd(195) | Pruning Register bit <4> of jump_count(4 downto 0) @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sat Sep 13 16:07:55 2008 ###########################################################] Synplicity Proasic Technology Mapper, Version 9.4.0, Build 055R, Built Jul 2 2008 07:11:59 Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved Product Version Version 9.4A1 @W:BN246 : | Failed to find top level module 'work.Top' as specified in project file @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Automatic dissolve during optimization of view:work.Analog_proc1_assc_wrapper(def_arch) of U0(ASSC) Automatic dissolve during optimization of view:work.Analog_proc1(def_arch) of Analog_proc1_assc_wrapper_inst(Analog_proc1_assc_wrapper) Automatic dissolve during optimization of view:work.Analog_proc1(def_arch) of Analog_proc1_assc_ram_inst(Analog_proc1_assc_ram) Automatic dissolve during optimization of view:work.grwzcnqmqzm(mjtkskcsjhk) of user_clk_sel(INITCFG_XF) Automatic dissolve during optimization of view:work.grwzcnqmqzm(mjtkskcsjhk) of valid_client(INITCFG_XE) Automatic dissolve during optimization of view:work.grwzcnqmqzm(mjtkskcsjhk) of address_gen(INITCFG_XD) Automatic dissolve during optimization of view:work.grwzcnqmqzm(mjtkskcsjhk) of user_control(INITCFG_XC) Automatic dissolve during optimization of view:work.grwzcnqmqzm(mjtkskcsjhk) of save_fsm(INITCFG_XB) Automatic dissolve during optimization of view:work.grwzcnqmqzm(mjtkskcsjhk) of init_fsm(INITCFG_XA) Automatic dissolve during optimization of view:work.NVM_sysm_init_wrapper(def_arch) of U0(INITCFG) Automatic dissolve during optimization of view:work.NVM_sysm(def_arch) of NVM_sysm_init_wrapper_inst(NVM_sysm_init_wrapper) Automatic dissolve at startup in view:work.Analog_proc1(def_arch) of Analog_proc1_abdelay_counter_inst(Analog_proc1_abdelay_counter) Automatic dissolve at startup in view:work.grwzcnqmqzm(mjtkskcsjhk) of user_clk_sel.u_jhmkpjjmdkx(jhmkpjjmdkx) @W:MO129 : initcfg_xf.vhd(29) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.bmnfdkrhvvn has been reduced to a combinational gate by constant propagation Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 88MB peak: 89MB) @N: : top.vhd(195) | Found counter in view:work.Top(rtl) inst jump_count[3:0] @N:MF176 : | Default generator successful Encoding state machine work.fmvgpwbdcxs(twzmfpzvmcf)-jzzdfrmzwdj[0:15] original code -> new code 0000000000000001 -> 0000000000000001 0000000000000010 -> 0000000000000010 0000000000000100 -> 0000000000000100 0000000000001000 -> 0000000000001000 0000000000010000 -> 0000000000010000 0000000000100000 -> 0000000000100000 0000000001000000 -> 0000000001000000 0000000010000000 -> 0000000010000000 0000000100000000 -> 0000000100000000 0000001000000000 -> 0000001000000000 0000010000000000 -> 0000010000000000 0000100000000000 -> 0000100000000000 0001000000000000 -> 0001000000000000 0010000000000000 -> 0010000000000000 0100000000000000 -> 0100000000000000 1000000000000000 -> 1000000000000000 @W:MO129 : assc.vhd(260) | Sequential instance Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[2] has been reduced to a combinational gate by constant propagation Encoding state machine work.stnpfdkggvx(zkzbcmxmrjf)-mwtvnzdkmwm[0:7] original code -> new code 00000001 -> 00000001 00000010 -> 00000010 00000100 -> 00000100 00001000 -> 00001000 00010000 -> 00010000 00100000 -> 00100000 01000000 -> 01000000 10000000 -> 10000000 Encoding state machine work.wbsfnwwctpn(mmwvfpfbppr)-crpwsdfhcqq[0:8] original code -> new code 000000001 -> 000000001 000000010 -> 000000010 000000100 -> 000000100 000001000 -> 000001000 000010000 -> 000010000 000100000 -> 000100000 001000000 -> 001000000 010000000 -> 010000000 100000000 -> 100000000 @W:MO129 : initcfg_xb.vhd(42) | Sequential instance NVM_inst.NVM_sysm_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[6] has been reduced to a combinational gate by constant propagation @W:MO150 : initcfg_xb.vhd(51) | Register big crpwsdfhcqq[8] is always 1, optimizing ... @W:MO150 : initcfg_xb.vhd(47) | Register big qmdjrgthbvj is always 0, optimizing ... @N: : initcfg_xd.vhd(47) | Found counter in view:work.dxwqxgdccxc(cmvhvtvbzkh) inst gnmdxrqrdgs[8:0] @N:MF176 : | Default generator successful @W:MO129 : initcfg_xf.vhd(32) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.zmbsbbtjszd has been reduced to a combinational gate by constant propagation Automatic dissolve during optimization of view:work.dxwqxgdccxc(cmvhvtvbzkh) of un1_dkjzqmrkvwb(ADD__const_cin_w13) Auto Dissolve of user_control.u_ffppvfwnggt (inst of view:work.ffppvfwnggt(zgctkkxfnjk)) Automatic dissolve during optimization of view:work.Top(rtl) of un3_count_1(PM_ADDC__0_2_AFS600_PQFP208_-2) Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 89MB) @N:BN116 : assc.vhd(199) | Removing sequential instance Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bcmkdjqtngz of view:PrimLib.dffr(prim) because there are no references to its outputs @N:BN116 : assc.vhd(216) | Removing sequential instance Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.ssssgmdwsms of view:PrimLib.dffr(prim) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 89MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 90MB) Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 89MB peak: 90MB) Finished Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 89MB peak: 90MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:04s; Memory used current: 89MB peak: 90MB) Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 92MB peak: 92MB) Promoting Net SYS_RESET_c on CLKBUF SYS_RESET_pad Promoting Net SYS_CLK_int on CLKINT I_73 Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 91MB peak: 92MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 91MB peak: 92MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 91MB peak: 92MB) Writing Analyst data base D:\Apps\app_notes\Fusion\improvedthroughput\throughput enhancement\Fusion_ADC_Throughput\Fusion_ADC_Throughput\synthesis\Top.srm @N:BN225 : | Writing default property annotation file D:\Apps\app_notes\Fusion\improvedthroughput\throughput enhancement\Fusion_ADC_Throughput\Fusion_ADC_Throughput\synthesis\Top.map. Finished Writing Netlist Databases (Time elapsed 0h:00m:04s; Memory used current: 91MB peak: 92MB) Writing EDIF Netlist and constraint files Version 9.4A1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 91MB peak: 92MB) Found clock Top|SYS_CLK with period 10.00ns Found clock Top|count_inferred_clock[1] with period 10.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Sat Sep 13 16:08:05 2008 # Top view: Top Library name: fusion Operating conditions: COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: fusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -5.874 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------- Top|SYS_CLK 100.0 MHz 46.0 MHz 10.000 21.748 -5.874 inferred Inferred_clkgroup_0 Top|count_inferred_clock[1] 100.0 MHz 77.7 MHz 10.000 12.875 -2.875 inferred Inferred_clkgroup_1 =================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------- Top|SYS_CLK Top|SYS_CLK | 10.000 -2.389 | 10.000 3.050 | 5.000 -5.874 | 5.000 0.182 Top|SYS_CLK Top|count_inferred_clock[1] | Diff grp - | No paths - | Diff grp - | Diff grp - Top|count_inferred_clock[1] Top|SYS_CLK | Diff grp - | No paths - | Diff grp - | Diff grp - Top|count_inferred_clock[1] Top|count_inferred_clock[1] | 10.000 -2.875 | No paths - | 5.000 0.459 | 5.000 3.524 ================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Top|SYS_CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 Top|SYS_CLK RAM4K9 DOUTB6 ASSC_RAM_DO_B_net[6] 2.375 -5.874 Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 Top|SYS_CLK RAM4K9 DOUTB7 ASSC_RAM_DO_B_net[7] 2.375 -5.790 NVM_inst.NVM_sysm_init_wrapper_inst.U0.u_grwzcnqmqzm.user_clk_sel.u_jhmkpjjmdkx.hrgmtcpsdzr Top|SYS_CLK DFN1C0 Q INIT_DONE_net 0.550 -4.575 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bksczsjcvgb Top|SYS_CLK DFN1E1C0 Q bksczsjcvgb 0.550 -4.325 Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 Top|SYS_CLK RAM4K9 DOUTB8 ASSC_RAM_DO_B_net[8] 2.375 -4.288 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[14] Top|SYS_CLK DFN1C0 Q jzzdfrmzwdj[14] 0.550 -3.742 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[3] Top|SYS_CLK DFN1C0 Q jzzdfrmzwdj[3] 0.434 -3.533 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[1] Top|SYS_CLK DFN1C0 Q jzzdfrmzwdj[1] 0.434 -3.431 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr Top|SYS_CLK DFN1C0 Q znbmnfdbzvr 0.550 -3.113 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[15] Top|SYS_CLK DFN1P0 Q jzzdfrmzwdj[15] 0.550 -3.003 =================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ jump_count[0] Top|SYS_CLK DFN0P0 D N_50_i_0_i_0 4.468 -5.874 ASSC_SEQCNTR_net[2] Top|SYS_CLK DFN0P0 D un1_ASSC_SEQCNTR_net_1_sqmuxa.N_17_i_i_0 4.468 -5.598 ASSC_SEQCNTR_net[5] Top|SYS_CLK DFN0C0 D un1_ASSC_SEQCNTR_net_1_sqmuxa.N_9 4.468 -5.284 ASSC_SEQCNTR_net[0] Top|SYS_CLK DFN0C0 D ASSC_SEQCNTR_net_RNO[0] 4.468 -5.276 ASSC_SEQCNTR_net[1] Top|SYS_CLK DFN0P0 D ASSC_SEQCNTR_net_RNO[1] 4.468 -5.276 ASSC_SEQCNTR_net[3] Top|SYS_CLK DFN0C0 D un1_ASSC_SEQCNTR_net_1_sqmuxa.N_18_i_i_0 4.468 -4.944 jump_count[1] Top|SYS_CLK DFN0E0C0 E N_43 4.546 -4.856 jump_count[2] Top|SYS_CLK DFN0E0C0 E N_43 4.546 -4.856 jump_count[3] Top|SYS_CLK DFN0E0C0 E N_43 4.546 -4.856 ASSC_SEQINSEL_net[0] Top|SYS_CLK DFN0C0 D N_47_i_i_0 4.468 -4.527 ============================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 10.342 = Slack (critical) : -5.874 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB6 Ending point: jump_count[0] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB6 Out 2.375 2.375 - ASSC_RAM_DO_B_net[6] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B B In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.469 4.068 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.952 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.460 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.701 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.089 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.329 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.826 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B B In - 8.050 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B Y Out 0.469 8.518 - N_43 Net - - 0.884 - 4 jump_count_RNO[0] XNOR2 B In - 9.402 - jump_count_RNO[0] XNOR2 Y Out 0.700 10.102 - N_50_i_0_i_0 Net - - 0.240 - 1 jump_count[0] DFN0P0 D In - 10.342 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.874 is 5.938(54.6%) logic and 4.936(45.4%) route. Path information for path number 2: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 10.258 = Slack (non-critical) : -5.790 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB7 Ending point: jump_count[0] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB7 Out 2.375 2.375 - ASSC_RAM_DO_B_net[7] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B A In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.384 3.983 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.867 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.376 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.616 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.004 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.245 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.742 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B B In - 7.966 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B Y Out 0.469 8.434 - N_43 Net - - 0.884 - 4 jump_count_RNO[0] XNOR2 B In - 9.318 - jump_count_RNO[0] XNOR2 Y Out 0.700 10.018 - N_50_i_0_i_0 Net - - 0.240 - 1 jump_count[0] DFN0P0 D In - 10.258 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.790 is 5.854(54.3%) logic and 4.936(45.7%) route. Path information for path number 3: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 10.066 = Slack (non-critical) : -5.598 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB6 Ending point: ASSC_SEQCNTR_net[2] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB6 Out 2.375 2.375 - ASSC_RAM_DO_B_net[6] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B B In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.469 4.068 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.952 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.460 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.701 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.089 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.329 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.826 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A A In - 8.050 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A Y Out 0.469 8.518 - N_29 Net - - 0.602 - 3 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C A In - 9.121 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C Y Out 0.705 9.825 - un1_ASSC_SEQCNTR_net_1_sqmuxa.N_17_i_i_0 Net - - 0.240 - 1 ASSC_SEQCNTR_net[2] DFN0P0 D In - 10.066 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.598 is 5.943(56.1%) logic and 4.654(43.9%) route. Path information for path number 4: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 9.981 = Slack (non-critical) : -5.513 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB7 Ending point: ASSC_SEQCNTR_net[2] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB7 Out 2.375 2.375 - ASSC_RAM_DO_B_net[7] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B A In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.384 3.983 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.867 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.376 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.616 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.004 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.245 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.742 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A A In - 7.966 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A Y Out 0.469 8.434 - N_29 Net - - 0.602 - 3 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C A In - 9.036 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C Y Out 0.705 9.741 - un1_ASSC_SEQCNTR_net_1_sqmuxa.N_17_i_i_0 Net - - 0.240 - 1 ASSC_SEQCNTR_net[2] DFN0P0 D In - 9.981 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.513 is 5.859(55.7%) logic and 4.654(44.3%) route. Path information for path number 5: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 9.752 = Slack (non-critical) : -5.284 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB6 Ending point: ASSC_SEQCNTR_net[5] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB6 Out 2.375 2.375 - ASSC_RAM_DO_B_net[6] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B B In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.469 4.068 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.952 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.460 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.701 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.089 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.329 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.826 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I21_Y_0_0_o2_m2_e NOR2A A In - 8.050 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I21_Y_0_0_o2_m2_e NOR2A Y Out 0.469 8.518 - ADD_6x6_fast_I21_Y_0_0_o2_m2_e Net - - 0.288 - 2 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I23_Y_0_i AX1C A In - 8.807 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I23_Y_0_i AX1C Y Out 0.705 9.511 - un1_ASSC_SEQCNTR_net_1_sqmuxa.N_9 Net - - 0.240 - 1 ASSC_SEQCNTR_net[5] DFN0C0 D In - 9.752 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.284 is 5.943(57.8%) logic and 4.340(42.2%) route. ==================================== Detailed Report for Clock: Top|count_inferred_clock[1] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 Top|count_inferred_clock[1] RAM4K9 DOUTB6 ASSC_RAM_DO_B_net[6] 2.375 -0.458 Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 Top|count_inferred_clock[1] RAM4K9 DOUTB7 ASSC_RAM_DO_B_net[7] 2.375 -0.354 NVM_inst.NVM_sysm_init_wrapper_inst.U0.u_grwzcnqmqzm.user_clk_sel.u_jhmkpjjmdkx.hrgmtcpsdzr Top|count_inferred_clock[1] DFN1C0 Q INIT_DONE_net 0.550 0.567 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bksczsjcvgb Top|count_inferred_clock[1] DFN1E1C0 Q bksczsjcvgb 0.550 1.940 Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 Top|count_inferred_clock[1] RAM4K9 DOUTB8 ASSC_RAM_DO_B_net[8] 2.375 -0.199 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[14] Top|count_inferred_clock[1] DFN1C0 Q jzzdfrmzwdj[14] 0.434 1.090 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[3] Top|count_inferred_clock[1] DFN1C0 Q jzzdfrmzwdj[3] 0.550 2.765 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[1] Top|count_inferred_clock[1] DFN1C0 Q jzzdfrmzwdj[1] 0.550 2.891 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr Top|count_inferred_clock[1] DFN1C0 Q znbmnfdbzvr 0.550 2.898 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj[15] Top|count_inferred_clock[1] DFN1P0 Q jzzdfrmzwdj[15] 0.434 3.109 =================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[2] INIT_DATA_net[2] 5.613 -2.875 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[4] INIT_DATA_net[4] 5.730 -2.687 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWEN INIT_ACM_WEN_OR_net 6.067 -2.609 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[1] INIT_DATA_net[1] 6.067 -2.438 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.hpvbctcvfcp[7] Top|count_inferred_clock[1] DFN1C0 D zpsvrxkccbh\.hpvbctcvfcp_4[7] 9.598 -2.389 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[0] INIT_DATA_net[0] 6.171 -2.367 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[7] INIT_DATA_net[7] 6.067 -2.346 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[3] INIT_DATA_net[3] 6.405 -2.067 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[5] INIT_DATA_net[5] 6.405 -2.029 Analog_inst.AB_INST Top|count_inferred_clock[1] AB ACMWDATA[6] INIT_DATA_net[6] 6.405 -2.020 ============================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 10.342 = Slack (critical) : -5.874 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB6 Ending point: jump_count[0] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB6 Out 2.375 2.375 - ASSC_RAM_DO_B_net[6] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B B In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.469 4.068 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.952 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.460 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.701 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.089 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.329 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.826 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B B In - 8.050 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B Y Out 0.469 8.518 - N_43 Net - - 0.884 - 4 jump_count_RNO[0] XNOR2 B In - 9.402 - jump_count_RNO[0] XNOR2 Y Out 0.700 10.102 - N_50_i_0_i_0 Net - - 0.240 - 1 jump_count[0] DFN0P0 D In - 10.342 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.874 is 5.938(54.6%) logic and 4.936(45.4%) route. Path information for path number 2: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 10.258 = Slack (non-critical) : -5.790 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB7 Ending point: jump_count[0] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB7 Out 2.375 2.375 - ASSC_RAM_DO_B_net[7] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B A In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.384 3.983 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.867 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.376 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.616 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.004 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.245 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.742 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B B In - 7.966 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.bnrsdrtmtsg_RNIUAN51[0] OR2B Y Out 0.469 8.434 - N_43 Net - - 0.884 - 4 jump_count_RNO[0] XNOR2 B In - 9.318 - jump_count_RNO[0] XNOR2 Y Out 0.700 10.018 - N_50_i_0_i_0 Net - - 0.240 - 1 jump_count[0] DFN0P0 D In - 10.258 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.790 is 5.854(54.3%) logic and 4.936(45.7%) route. Path information for path number 3: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 10.066 = Slack (non-critical) : -5.598 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB6 Ending point: ASSC_SEQCNTR_net[2] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB6 Out 2.375 2.375 - ASSC_RAM_DO_B_net[6] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B B In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.469 4.068 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.952 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.460 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.701 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.089 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.329 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.826 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A A In - 8.050 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A Y Out 0.469 8.518 - N_29 Net - - 0.602 - 3 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C A In - 9.121 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C Y Out 0.705 9.825 - un1_ASSC_SEQCNTR_net_1_sqmuxa.N_17_i_i_0 Net - - 0.240 - 1 ASSC_SEQCNTR_net[2] DFN0P0 D In - 10.066 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.598 is 5.943(56.1%) logic and 4.654(43.9%) route. Path information for path number 4: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 9.981 = Slack (non-critical) : -5.513 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB7 Ending point: ASSC_SEQCNTR_net[2] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB7 Out 2.375 2.375 - ASSC_RAM_DO_B_net[7] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B A In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.384 3.983 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.867 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.376 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.616 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.004 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.245 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.742 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A A In - 7.966 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNIRCC21[0] NOR2A Y Out 0.469 8.434 - N_29 Net - - 0.602 - 3 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C A In - 9.036 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I20_Y_0_0_x2 AX1C Y Out 0.705 9.741 - un1_ASSC_SEQCNTR_net_1_sqmuxa.N_17_i_i_0 Net - - 0.240 - 1 ASSC_SEQCNTR_net[2] DFN0P0 D In - 9.981 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.513 is 5.859(55.7%) logic and 4.654(44.3%) route. Path information for path number 5: Requested Period: 5.000 - Setup time: 0.532 = Required time: 4.468 - Propagation time: 9.752 = Slack (non-critical) : -5.284 Number of logic level(s): 6 Starting point: Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 / DOUTB6 Ending point: ASSC_SEQCNTR_net[5] / D The start point is clocked by Top|SYS_CLK [rising] on pin CLKB The end point is clocked by Top|SYS_CLK [falling] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------ Analog_inst.Analog_proc1_assc_ram_inst.Analog_proc1_assc_ram_R0C0 RAM4K9 DOUTB6 Out 2.375 2.375 - ASSC_RAM_DO_B_net[6] Net - - 1.224 - 8 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B B In - 3.599 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.cmbpphsszmt_a1_4_3 OR2B Y Out 0.469 4.068 - N_435 Net - - 0.884 - 4 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B C In - 4.952 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.znbmnfdbzvr_RNIB8D6_0 OR3B Y Out 0.509 5.460 - cmbpphsszmt_a1_4 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 A In - 5.701 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNI7E7H[15] AO1 Y Out 0.388 6.089 - cmbpphsszmt_1 Net - - 0.240 - 1 Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C C In - 6.329 - Analog_inst.Analog_proc1_assc_wrapper_inst.U0.u_fmvgpwbdcxs.jzzdfrmzwdj_RNID4011[0] OR3C Y Out 0.497 6.826 - ASSC_SEQCHANGE_net Net - - 1.224 - 8 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I21_Y_0_0_o2_m2_e NOR2A A In - 8.050 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I21_Y_0_0_o2_m2_e NOR2A Y Out 0.469 8.518 - ADD_6x6_fast_I21_Y_0_0_o2_m2_e Net - - 0.288 - 2 un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I23_Y_0_i AX1C A In - 8.807 - un1_ASSC_SEQCNTR_net_1_sqmuxa.ADD_6x6_fast_I23_Y_0_i AX1C Y Out 0.705 9.511 - un1_ASSC_SEQCNTR_net_1_sqmuxa.N_9 Net - - 0.240 - 1 ASSC_SEQCNTR_net[5] DFN0C0 D In - 9.752 - ====================================================================================================================================================== Total path delay (propagation time + setup) of 10.284 is 5.943(57.8%) logic and 4.340(42.2%) route. ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Report for cell Top.rtl Core Cell usage: cell count area count*area AND2 36 1.0 36.0 AND2A 1 1.0 1.0 AND3 10 1.0 10.0 AO1 16 1.0 16.0 AO1A 3 1.0 3.0 AO1B 4 1.0 4.0 AO1C 2 1.0 2.0 AOI1 2 1.0 2.0 AOI1B 1 1.0 1.0 AX1A 1 1.0 1.0 AX1C 4 1.0 4.0 AX1E 2 1.0 2.0 CLKINT 1 0.0 0.0 GND 23 0.0 0.0 INV 5 1.0 5.0 MX2 14 1.0 14.0 MX2C 23 1.0 23.0 NOR2 12 1.0 12.0 NOR2A 57 1.0 57.0 NOR2B 28 1.0 28.0 NOR3 1 1.0 1.0 NOR3A 6 1.0 6.0 NOR3B 11 1.0 11.0 NOR3C 11 1.0 11.0 OA1 3 1.0 3.0 OA1A 2 1.0 2.0 OA1B 3 1.0 3.0 OAI1 2 1.0 2.0 OR2 14 1.0 14.0 OR2A 13 1.0 13.0 OR2B 11 1.0 11.0 OR3A 6 1.0 6.0 OR3B 3 1.0 3.0 OR3C 2 1.0 2.0 VCC 23 0.0 0.0 XA1 1 1.0 1.0 XA1A 2 1.0 2.0 XA1B 6 1.0 6.0 XA1C 3 1.0 3.0 XNOR2 4 1.0 4.0 XOR2 48 1.0 48.0 ZOR3 2 1.0 2.0 DFN0C0 5 1.0 5.0 DFN0E0C0 3 1.0 3.0 DFN0E1C0 2 1.0 2.0 DFN0P0 4 1.0 4.0 DFN1C0 53 1.0 53.0 DFN1E0C0 7 1.0 7.0 DFN1E1C0 71 1.0 71.0 DFN1P0 3 1.0 3.0 NVM 1 0.0 0.0 RAM4K9 1 0.0 0.0 ----- ---------- TOTAL 572 523.0 IO Cell usage: cell count AB 1 CLKBUF 1 INBUF 2 INBUF_A 18 OUTBUF 24 ----- TOTAL 46 Core Cells : 523 of 13824 (4%) IO Cells : 46 of 172 (27%) RAM/ROM Usage Summary Block Rams : 1 of 24 (4%) Mapper successful! Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Sat Sep 13 16:08:05 2008 ###########################################################]