-- ********************************************************************** -- -- FILE : zl38004qc.bsd -- generated by Cz.P. as zl38004 on Thu Jul 5 09:41:23 EDT 2007 -- using p.jtag.bsd rev 3.5 - 9 May, 2007 -- -- BSDL description for top level entity zl38004 -- Device : ZL38004 Enhanced Voice Processor with Dual Codecs -- Package : 100-Pin LQFP -- -- Number of BSC cells: 65 -- -- ********************************************************************** -- Modification History: -- Revision 1.0: Thu Jul 5 09:41:23 EDT 2007 -- - Clarified IC_OPEN -- Initial release: Wed May 3 14:51:35 EDT 2006 -- ********************************************************************** -- -- IMPORTANT NOTICE -- -- This information is for modeling purposes only, and is not guaranteed. -- -- This information is provided "as is" without warranty of any kind. -- It may contain technical inaccuracies or typographical errors. -- -- ZARLINK and ZL38004 are trademarks of ZARLINK Semiconductor. ZARLINK -- products, marketed under trademarks, are protected under numerous US -- and foreign patents and pending applications, maskwork rights, and -- copyrights. -- -- ZARLINK reserves the right to make changes to any products and -- services at any time without notice. ZARLINK assumes no -- responsibility or liability arising out of the application or use of -- any information, product, or service described herein except as -- expressly agreed to in writing by ZARLINK Corporation. ZARLINK -- customers are advised to obtain the latest version of device -- specifications before relying on any published information and before -- placing orders for products or services. -- -- ====================================================================== -- This BSDL model has been validated for syntax and semantics compliance -- to IEEE 1149.1 using ASSET/Agilent BSDL Validation Service. -- ====================================================================== -- -- ******************************************************************** -- -- SPECIAL NOTES -- -- 1. All instruction opcodes other than those defined in this file -- should be considered PRIVATE. -- -- 2. IC_GND - tie low for normal operation -- -- 3. IC_OPEN1, IC_OPEN2 - Internal Connect. Leave open for normal operation. -- -- ******************************************************************** entity zl38004 is generic(PHYSICAL_PIN_MAP : string := "LQFP_PACKAGE"); port ( AGUARD: linkage bit; BIAS_RF_M: linkage bit; BIAS_RF_P: linkage bit; BIAS_VCM: linkage bit; C0_ADCI_M: linkage bit; C0_ADCI_P: linkage bit; C0_BFO_M: linkage bit; C0_BFO_P: linkage bit; C0_DACO_M: linkage bit; C0_DACO_P: linkage bit; C1_ADCI_M: linkage bit; C1_ADCI_P: linkage bit; C1_BFO_M: linkage bit; C1_BFO_P: linkage bit; C1_DACO_M: linkage bit; C1_DACO_P: linkage bit; DGUARD: linkage bit; GPIO: inout bit_vector (0 to 10); I2S_LRCK: inout bit; I2S_MCLK: inout bit; I2S_SCK: inout bit; I2S_SD_IO: inout bit; I2S_SDI: in bit; IC_GND: linkage bit; IC_OPEN1: linkage bit; IC_OPEN2: linkage bit; NC: linkage bit_vector (1 to 13); OSCI: linkage bit; OSCO: linkage bit; PCM_CLKI: in bit; PCM_CLKO: out bit; PCM_LBCI: in bit; PENA2: inout bit; PFPB_PENA1: inout bit; PPCMI: in bit; PPCMO: out bit; RST_B: in bit; SPIM_CLK: out bit; SPIM_CS_B0: out bit; SPIM_CS_B1: out bit; SPIM_MISO: in bit; SPIM_MOSI: out bit; SPIS_CLK: in bit; SPIS_CS_B: in bit; SPIS_MISO: out bit; SPIS_MOSI: in bit; TCK: in bit; TDI: in bit; TDO: out bit; TMS: in bit; TRST_B: in bit; UART_RX: in bit; UART_TX: out bit; AVDD_APLL: linkage bit; AVSS_APLL: linkage bit; C0_AVDD: linkage bit; C0_AVSS: linkage bit; C1_AVDD: linkage bit; C1_AVSS: linkage bit; DVDD_APLL: linkage bit; DVSS_APLL: linkage bit; VDD_CORE: linkage bit_vector (1 to 3); VDD_DPLL: linkage bit; VDD_IO: linkage bit_vector (1 to 3); VDD_OSC: linkage bit; VDD_OSC_IO: linkage bit; VSS_CORE: linkage bit_vector (1 to 3); VSS_DPLL: linkage bit; VSS_IO: linkage bit_vector (1 to 3); VSS_OSC: linkage bit ); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of zl38004 : entity is "STD_1149_1_2001"; attribute PIN_MAP of zl38004 : entity is PHYSICAL_PIN_MAP; constant LQFP_PACKAGE : PIN_MAP_STRING := "AGUARD : 86 , " & "BIAS_RF_M : 89 , " & "BIAS_RF_P : 88 , " & "BIAS_VCM : 87 , " & "C0_ADCI_M : 83 , " & "C0_ADCI_P : 84 , " & "C0_BFO_M : 85 , " & "C0_BFO_P : 82 , " & "C0_DACO_M : 79 , " & "C0_DACO_P : 78 , " & "C1_ADCI_M : 94 , " & "C1_ADCI_P : 93 , " & "C1_BFO_M : 92 , " & "C1_BFO_P : 95 , " & "C1_DACO_M : 98 , " & "C1_DACO_P : 99 , " & "DGUARD : 7 , " & "GPIO :(21 , " & -- GPIO[0] "22 , " & -- GPIO[1] "23 , " & -- GPIO[2] "27 , " & -- GPIO[3] "28 , " & -- GPIO[4] "29 , " & -- GPIO[5] "30 , " & -- GPIO[6] "44 , " & -- GPIO[7] "45 , " & -- GPIO[8] "46 , " & -- GPIO[9] "47 ), " & -- GPIO[10] "I2S_LRCK : 18 , " & "I2S_MCLK : 15 , " & "I2S_SCK : 12 , " & "I2S_SD_IO : 19 , " & "I2S_SDI : 20 , " & "IC_GND : 9 , " & "IC_OPEN1 : 91 , " & "IC_OPEN2 : 90 , " & "NC :(1 , " & -- NC[1] "24 , " & -- NC[2] "25 , " & -- NC[3] "26 , " & -- NC[4] "49 , " & -- NC[5] "50 , " & -- NC[6] "51 , " & -- NC[7] "52 , " & -- NC[8] "61 , " & -- NC[9] "75 , " & -- NC[10] "76 , " & -- NC[11] "77 , " & -- NC[12] "100 ), " & -- NC[13] "OSCI : 70 , " & "OSCO : 69 , " & "PCM_CLKI : 65 , " & "PCM_CLKO : 55 , " & "PCM_LBCI : 62 , " & "PENA2 : 48 , " & "PFPB_PENA1 : 57 , " & "PPCMI : 60 , " & "PPCMO : 56 , " & "RST_B : 8 , " & "SPIM_CLK : 37 , " & "SPIM_CS_B0 : 41 , " & "SPIM_CS_B1 : 42 , " & "SPIM_MISO : 43 , " & "SPIM_MOSI : 38 , " & "SPIS_CLK : 34 , " & "SPIS_CS_B : 32 , " & "SPIS_MISO : 33 , " & "SPIS_MOSI : 31 , " & "TCK : 5 , " & "TDI : 3 , " & "TDO : 6 , " & "TMS : 4 , " & "TRST_B : 2 , " & "UART_RX : 10 , " & "UART_TX : 11 , " & "AVDD_APLL : 74 , " & "AVSS_APLL : 73 , " & "C0_AVDD : 80 , " & "C0_AVSS : 81 , " & "C1_AVDD : 97 , " & "C1_AVSS : 96 , " & "DVDD_APLL : 72 , " & "DVSS_APLL : 71 , " & "VDD_CORE :(14, 40, 59)," & "VDD_DPLL : 64 , " & "VDD_IO :(17, 36, 54)," & "VDD_OSC : 66 , " & "VDD_OSC_IO : 68 , " & "VSS_CORE :(13, 39, 58)," & "VSS_DPLL : 63 , " & "VSS_IO :(16, 35, 53)," & "VSS_OSC : 67"; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6,BOTH); attribute TAP_SCAN_RESET of TRST_B : signal is true; -- -- NOTE: All instruction opcodes other than those defined in this file -- should be considered PRIVATE. -- attribute INSTRUCTION_LENGTH of zl38004 : entity is 17; attribute INSTRUCTION_OPCODE of zl38004 : entity is "bypass (00000000000000000)," & "bypass (11111111111111111)," & "clamp (11111111111101111)," & "extest (11111111111101000)," & "highz (11111111111001111)," & "idcode (11111111111111110)," & "preload (11111111111111000)," & "sample (11111111111111000)"; attribute INSTRUCTION_CAPTURE of zl38004 : entity is "xxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of zl38004 : entity is "0001" & -- version "1001010001110100" & -- part number "00010100101" & -- manufacturer id "1"; attribute REGISTER_ACCESS of zl38004 : entity is "boundary (extest, sample, preload)," & "bypass (bypass, clamp, highz)," & "device_id (idcode)" ; attribute BOUNDARY_LENGTH of zl38004 : entity is 65; attribute BOUNDARY_REGISTER of zl38004 : entity is -- num cell port function safe ccel disval rslt " 0 ( BC_0, *, internal, X) ," & " 1 ( BC_4, RST_B, input, X) ," & " 2 ( BC_4, UART_RX, input, X) ," & " 3 ( BC_2, UART_TX, output3, X, 4, 1, Z) ," & " 4 ( BC_2, *, control, 1) ," & " 5 ( BC_7, I2S_SCK, bidir, X, 6, 1, Z) ," & " 6 ( BC_2, *, control, 1) ," & " 7 ( BC_7, I2S_MCLK, bidir, X, 8, 1, Z) ," & " 8 ( BC_2, *, control, 1) ," & " 9 ( BC_0, *, internal, X) ," & " 10 ( BC_7, I2S_LRCK, bidir, X, 11, 1, Z) ," & " 11 ( BC_2, *, control, 1) ," & " 12 ( BC_7, I2S_SD_IO, bidir, X, 13, 1, Z) ," & " 13 ( BC_2, *, control, 1) ," & " 14 ( BC_4, I2S_SDI, input, X) ," & " 15 ( BC_7, GPIO(0), bidir, X, 16, 1, Z) ," & " 16 ( BC_2, *, control, 1) ," & " 17 ( BC_7, GPIO(1), bidir, X, 18, 1, Z) ," & " 18 ( BC_2, *, control, 1) ," & " 19 ( BC_7, GPIO(2), bidir, X, 20, 1, Z) ," & " 20 ( BC_2, *, control, 1) ," & " 21 ( BC_7, GPIO(3), bidir, X, 22, 1, Z) ," & " 22 ( BC_2, *, control, 1) ," & " 23 ( BC_7, GPIO(4), bidir, X, 24, 1, Z) ," & " 24 ( BC_2, *, control, 1) ," & " 25 ( BC_7, GPIO(5), bidir, X, 26, 1, Z) ," & " 26 ( BC_2, *, control, 1) ," & " 27 ( BC_7, GPIO(6), bidir, X, 28, 1, Z) ," & " 28 ( BC_2, *, control, 1) ," & " 29 ( BC_4, SPIS_MOSI, input, X) ," & " 30 ( BC_4, SPIS_CS_B, input, X) ," & " 31 ( BC_2, SPIS_MISO, output3, X, 32, 1, Z) ," & " 32 ( BC_2, *, control, 1) ," & " 33 ( BC_4, SPIS_CLK, input, X) ," & " 34 ( BC_0, *, internal, X) ," & " 35 ( BC_2, SPIM_CLK, output3, X, 36, 1, Z) ," & " 36 ( BC_2, *, control, 1) ," & " 37 ( BC_2, SPIM_MOSI, output3, X, 38, 1, Z) ," & " 38 ( BC_2, *, control, 1) ," & " 39 ( BC_0, *, internal, X) ," & " 40 ( BC_2, SPIM_CS_B0, output3, X, 41, 1, Z) ," & " 41 ( BC_2, *, control, 1) ," & " 42 ( BC_2, SPIM_CS_B1, output3, X, 43, 1, Z) ," & " 43 ( BC_2, *, control, 1) ," & " 44 ( BC_4, SPIM_MISO, input, X) ," & " 45 ( BC_7, GPIO(7), bidir, X, 46, 1, Z) ," & " 46 ( BC_2, *, control, 1) ," & " 47 ( BC_7, GPIO(8), bidir, X, 48, 1, Z) ," & " 48 ( BC_2, *, control, 1) ," & " 49 ( BC_7, GPIO(9), bidir, X, 50, 1, Z) ," & " 50 ( BC_2, *, control, 1) ," & " 51 ( BC_7, GPIO(10), bidir, X, 52, 1, Z) ," & " 52 ( BC_2, *, control, 1) ," & " 53 ( BC_7, PENA2, bidir, X, 54, 1, Z) ," & " 54 ( BC_2, *, control, 1) ," & " 55 ( BC_0, *, internal, X) ," & " 56 ( BC_2, PCM_CLKO, output3, X, 57, 1, Z) ," & " 57 ( BC_2, *, control, 1) ," & " 58 ( BC_2, PPCMO, output3, X, 59, 1, Z) ," & " 59 ( BC_2, *, control, 1) ," & " 60 ( BC_7, PFPB_PENA1, bidir, X, 61, 1, Z) ," & " 61 ( BC_2, *, control, 1) ," & " 62 ( BC_4, PPCMI, input, X) ," & " 63 ( BC_4, PCM_LBCI, input, X) ," & " 64 ( BC_4, PCM_CLKI, input, X) "; end zl38004; ------------- end of BSDL description for the zl38004 ----------