Application Notes
Documents
Document Name | Size | Published | Modified | |
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5-5-PDVMeasurementAndLimits-Wertheimer | 621.89 kB | 02/18/2013 | 03/02/2013 | |
A Closer Look at PDV and Oscillator for Packet Equipment Clocks
Describes the requirements and differences between traditional equipment clocks (ECs) and packet equipment clocks (PECs), the packet delay variation (PDV) metric and the impact of local oscillator (XO) selection for systems in packet networks.
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705.16 kB | 02/14/2013 | 02/14/2013 | |
Ab5364-appnote | 168.79 kB | 02/16/2013 | 03/09/2017 | |
AN SLIC SurgeProtect B2 ID080270-sept07 | 136.64 kB | 02/15/2013 | 02/15/2013 | |
An178-appnote | 200.53 kB | 02/15/2013 | 02/15/2013 | |
AN4391 - Implement Master-Slave Timing-Card Redundancy | 273.58 kB | 09/26/2014 | 09/26/2014 | |
An5207-appnote | 153.13 kB | 02/15/2013 | 02/15/2013 | |
An5783-appnote | 126.65 kB | 02/15/2013 | 02/15/2013 | |
Appendix | 203.3 kB | 02/15/2013 | 02/15/2013 | |
Day 1 1550 Microsemi Wertheimer | 404.58 kB | 02/15/2013 | 02/15/2013 | |
Deploying SyncE and IEEE 1588 in Wireless Backhaul
Presented at the Workshop on Synchronization in Telecommunication Systems (WSTS) in 2012, this paper shows the evolution from generic switched network to a packet switched network and its impact on wireless basestations with synchronization of both frequency and phase being provided by the convergence of IEEE 1588 and SyncE.
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3.1 MB | 02/14/2013 | 02/14/2013 | |
Esd-appnote | 932.94 kB | 02/15/2013 | 02/15/2013 | |
From Complicated to Simple with Single-Chip Silicon Clock Generation
Describing the advantages of a single-chip silicon clock generation solution for the effective management and control of dataflow across multiple components for a wide range of applications.
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221.49 kB | 02/14/2013 | 02/14/2013 | |
IEEE 1588 Packet Network Synchronization Solution
Presented at the Freescale Technology Forum - China (FTF) in 2011, this paper describes the evolution of synchronization in 2G/3G and 4G/LTE networks, the standards, the convergence of IEEE 1588 and SyncE, and considerations for hardware and software architectures when implementing IEEE and SyncE for multiple applications.
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570.46 kB | 02/14/2013 | 02/14/2013 | |
IEEE-1588 and Synchronous Ethernet ‰ÛÒ the Whole is Greater Than Its Parts
Presented at the International Telecom Sync Forum ( ITSF) conference in 2012, this paper describes extension of the SONET/SDH timing model of frequency distribution using SyncE and when combined with IEEE-1588 to provide superior timing performance in the network.
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288.65 kB | 02/14/2013 | 02/15/2013 | |
Interpreting-Amplitude-Ripple-Appnote | 423.56 kB | 02/15/2013 | 02/15/2013 | |
Microsemi Clock Generators for Altera FPGAs
Microsemi Clock Generators for Altera FPGAs
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318.73 kB | 07/19/2019 | 07/19/2019 | |
Microsemi Clock Generators for SMART Fusion and IGLOO FPGAs
Microsemi Clock Generators for SMART Fusion and IGLOO FPGAs
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312.83 kB | 07/19/2019 | 07/19/2019 | |
Microsemi Clock Generators for Xilinx FPGAs
Microsemi Clock Generators for Xilinx FPGAs
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389.13 kB | 07/19/2019 | 07/19/2019 | |
Microsemi Z-Star Protocol Standard (App Note) | 385.8 kB | 11/16/2016 | 11/16/2016 |