| Time | Class | Track |
| 11 am | Hybrid ESL/RTL co-verification platform for system level software testing | SoC Architecture & Analysis |
| 11 am | ARM nSTEP Microcontroller Implementation Using Cadence Silicon Realization Flows in Samsung 20nm Technology | SoC Design & Verification |
| 11 am | Enabling a Full System View: Bridging Software and Hardware Debug Infrastructures to Accelerate the Verification and Validation of SoCs | SoC Design & Verification |
| 11 am | Flow and tools, tips and tricks: Implementing successful Cortex-A15-based designs | SoC Design for Power & Performance |
| 11 am | Increasing IP Quality through Register Management | SoC IP |
| 12 pm | SoC Architecture & Analysis | SoC IP |
| 12 pm | End-to-End Quality of Service in Multicore SoC Design | SoC Architecture & Analysis |
| 12 pm | Managing the Complexity of Double Patterning to Enable Cost-Effective Scaling into the Sub-resolution Domain | SoC Design & Verification |
| 12 pm | Resolving complex multi-core resource sharing through queue and traffic management | SoC Design & Verification |
| 12 pm | Integrated Silicon MEMS Resonators Simplify Design of Timing Subsystems | SoC IP |
| 2:10 pm | A Parametric Approach for Handling Local Process Variation Effects in Timing Analysis | SoC Architecture & Analysis |
| 2:10 pm | Architecture Analysis of a Multi-Mode Base-Station Chipset | SoC Architecture & Analysis |
| 2:10 pm | Creating an Effective 28nm ARM SoC Design Methodology: Addressing Design Complexity, Timing Variability and Silicon Manufacturability Challenges | SoC Design & Verification |
| 2:10 pm | Low power design - what's next after basic power gating? | SoC Design for Power & Performance |
| 2:10 pm | ARM Cortex-M Processor System Design - Getting to silicon faster with Cortex-M processors | SoC IP |
| 3:10 pm | DDR4, HIgher Speds and Larger SoCs: Why External Memory Latency Is Getting Worse, And What To Do About It | SoC Architecture & Analysis |
| 3:10 pm | Working towards exploiting the different SRAM #T cells within the context of an ARM core | SoC Architecture & Analysis |
| 3:10 pm | Modeling and Verifying Cache-Coherent Protocols, VIP, and Designs | SoC Design & Verification |
| 3:10 pm | Multi-Gate MOSFET Technology and Models for the 14nm node | SoC Design & Verification |
| 3:10 pm | ESL Multicore-ARM Design & Verification for Power & Performance | SoC Design for Power & Performance |
| 4:10 pm | Performance Analysis of the Cortex A15 with AXI4 | SoC Architecture & Analysis |
| 4:10 pm | Formal Verification of RTL changes for IP Hardening | SoC Design & Verification |
| 4:10 pm | Graph-Based IP Verification in an ARM SoC Environment | SoC Design & Verification |
| 4:10 pm | Solving complex SoC implementation challenges with ARM Hard Macros | SoC Design for Power & Performance |
| 4:10 pm | How to Leverage AMBA 4 in Next-Generation SoC Designs | SoC IP |