Register here for one of our booth sessions.
Meet Us at Flash Memory Summit
Come hear our experts and learn about High Performance, Scalable NVMe Dual-Host Failover Architecture, Switchtec PAX Advanced
PCIe Storage Switches, next generation Flashtec
NVMe controllers and Flashtec
NVRAM Drives. We look forward to seeing you at Booth #213.
"EmPowering PCIe Storage" Sessions at the Microsemi Booth
Microsemi will be hosting seven core sessions at booth #213 that you won’t want to miss. To register
, click here.The first five online registrations for each session will receive a free gift onsite (session attendance is required.)
Session 1: Security in NVMe Enterprise SSD
Securely storing, transferring, and retrieving data without impacting the performance has become the most important need for NVMe SSD solutions in the Enterprise market. There are standards such as FIPS and TCG that define the standards of security for an NVMe SSD. In this presentation, I will briefly discuss these standards and also define the requirements to securely transfer, store, and retrieve the data in an NVMe enterprise SSD.
Session 2: Will Mainstream PCIe SSDs End SATA SSD Adoption in Enterprise?
This paper examines the reasons behind the transition from SATA to PCIe in volume mainstream enterprise SSDs. Examined issues will include:
- Performance difference between SATA and PCIe mainstream enterprise SSDs
- Mainstream enterprise SSD requirements that have evolved beyond low cost alone and include features such as SRIOV, PCIe dual port, and SRIS
- The impact of NAND roadmaps and what capacities are going to be feasible and practical for mainstream SSDs
Session 3: Roles of SDRAMs in the Development of Enterprise SSDs and Best Practices
In an Enterprise SSD, SDRAM plays a vital role in meeting the demands of enterprise-class features such as performance and reliability. Designing an Enterprise SSD with SDRAM has its own challenges and tricks to make the best use of it. This presentation will cover the roles and best practices of SDRAMs including factors that need to be considered in choosing the SDRAM controller features, PCB design, and calibration debug/troubleshooting techniques.
Session 4: Gen-Z. . . Unleashing the Potential of Memory Centric Architecture!
Data center machine learning and analytic workloads require ever greater scalability performance from computing, memory and storage infrastructure solutions. Gen-Z enables memory to scale with CPU performance, allows for a new level of resource pooling efficiency and will unleash the full potential of emerging storage class memory technology. Microsemi endorses the open Gen-Z standard and the industrywide innovation it can deliver. Our portfolio of fabric, data protection and security technologies positions Microsemi well to deliver Gen-Z product solutions. This presentation will include an overview of Gen-Z technology and key applications.
Session 5: SSD Lifetime Extension Using Multi-Code-Rate LDPC with Multi-Dimensional LLR Tables
From the early days, NAND flash memories have strongly leveraged error correction code techniques to improve reliability. The most recent SSD controllers embed low density parity check (LDPC) codes. Indeed, among the codes that can be effectively integrated on a small piece of silicon, LDPC is definitely the one that gets closer to the Shannon limit. LDPC performance is strongly influenced by the code rate (the amount of parity bits spent for correction) and by the quality of LLR tables (that affect performances of soft decoding). This presentation describes a flexible flash controller architecture, developed to handle multiple code rates with multi-dimensional LLR tables. This approach allows optimizing correction performances at the minimum cost, thus maximizing the lifetime of a solid state drive.
Session 6: PCIe/NVMe Hot Plug with Switchtec
With the rapid adoption of low-latency PCIe in the data center, a new class of challenges are born. Hot plug of PCIe NVMe SSDs is a de-facto use-case, management of the PCIe switch is an expectation, and industry adoption of a standardized mechanism is required. This presentation will address these three challenges by de-mystifying hot plug in PCIe, discussing how Switchtec simplifies PCIe hot plug, providing an open source lightweight switch management driver, and an open source user-space utility.
Session 7: IOPS and QoS Analysis of DRAM-based and 1 Gb All-MRAM-based NVRAM Cards
PCIe DRAM-based non-volatile RAM (NVRAM) cards are gaining traction in the market because they can be used either as a very fast and secure synchronous write buffer or to store both critical system data and user data in case of power failure. In a nutshell, the host sees the NVRAM card as a bunch of DRAM devices connected over a PCIe bus. If the power suddenly disappears, the on-board controller copies the DRAM content to a bank of flash memories. During this copy operation, a super capacitor supplies the necessary energy. MRAM memories are now mature enough to offer a technically viable alternative to the combination of DRAM and flash, removing the need for a super capacitor because of the MRAM inherent non-volatility.
In this work, we present a thorough analysis of IOPS and latency (QoS) for both DRAM/flash-based and all-MRAM NVRAM cards. Results of simulations indicate that MRAM NVRAM cards can compete with legacy DRAM/flash cards, at least when looking at performance figures such as random read/write IOPS and latency.
For more information please visit the Flash Memory Summit website.