EE Times recently published a short discussion on the advantages of processors using the RISC-V open instruction set architecture (ISA) in Aerospace and Defense applications. The advantages offered Read more »
Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.
The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention Read more »
Editor’s Note: A May 2018 announcement by Microsemi of its collaboration with fabless semiconductor company SiFive, aimed at enabling Linux software and firmware developers to build RISC-V PCs, offered the opportunity Read more »
The April 2018 edition of SatNews magazine published an article by Ted Marena and Ken O’Neill from Microsemi that discussed the advantages of using processors based upon the RISC-V open instruction set architecture. The article looks at Read more »
RISC-V MEETUP
Plan to attend the inaugural Rocky Mountain RISC-V Meetup – Read more »
This article explores the benefits behind RISC-V’s open-source hardware model, discussing it’s longevity, portability, and reliability.
The momentum behind RISC-V for embedded applications is undeniable. Read more »
Arrow and Microsemi are hosting a series of hands-on workshops featuring Microsemi’s low-power, cost-optimized, mid-range PolarFire™ FPGAs and Arrow’s new low-cost Everest Development Kit.Read more »
Antmicro, the maker of the open-source Renode framework for multi-node simulation, has implemented support for Microsemi’s Mi-V™, RISC-V-based soft central processing units (CPUs) and the solution’s integration with Read more »
Designers face many unique challenges when developing systems used in space that do not exist for terrestrial systems.
Among these are the need to ensure the trustworthiness Read more »
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