We are rounding up our Clock Jitter series by taking a look at what external factors can induce jitter in oscillators, and how they can be effectively compensated for.Read more »
Continuous advances in high-speed communication and measurement systems require higher levels of performance from system clocks and references.Read more »
As previously demonstrated, timing noise/jitter is a very complicated phenomenon, and in order to understand how jitter can impact a system it needs to be measured and quantified. Read more »
In a previous post we described Power Supply Rejection Ratio (PSRR) and discussed the ways it can impact an oscillators performance. In this update one of the ways we approach measuring PSRR on our devices.Read more »
Power Supply Rejection Ratio or Power Supply Ripple Rejection (PSRR) is a measure of how well a circuit rejects noise, of various frequencies, injected at its voltage input. The ripple can be induced from a number of sources, such as a 50Hz/60Hz supply ripple, a switching ripple from a DC/DC converter, or a ripple due to the sharing of an input supply between different circuit blocks on the board. In the timing solutions world, when discussing PSRR we are typically referring to supply ripple.
Holdover is what happens when the primary timing reference goes away for some reason and the local oscillator is left to its own devices (for a fairly well maintained summary of the topic see the Wikipedia article Holdover in synchronization applications)
The question is: How much can you trust the local oscillator and for how long?
There is a lot of information available on the internet for engineers who want to learn more about frequency control, synchronization and clocks in general.
