EE Times recently published a short discussion on the advantages of processors using the RISC-V open instruction set architecture (ISA) in Aerospace and Defense applications. The advantages offered by this open ISA to optimize utilization and performance, and the availability of inspectable code, are particularly important for space applications. The article is published on the EE Times website.

For further information, please contact ken.o’neill@microchip.com

Tags: Aerospace, Defense, EE Times, FPGAs, Instruction Set Architecture, ISA, RISC-V, Space