Chip Scale Atomic Clocks: Effects on Timing Error – Initial Frequency Offset (Part 4 of 4)

Initial phase and frequency errors an have a big impact on holdover performance. The CSAC’s unique 1PPS input can be utilized to eliminate these errors by employing proper disciplining.

From equation 1 (see part 2 of this series), we can see that if a CSAC is not adequately disciplined to a superior reference prior to entering the holdover period, any frequency offset y0 will be multiplied by the holdover duration t.

The following graph shows an example where we have taken the CSAC_1 sample data from our rapid temperature test and inserted various frequency offsets at the beginning of the data set.

The corresponding phase data is shown, as follows. An initial offset of 5 x 10–10 and 1 x 10–9 Hz/Hz produced 10.5 μs and 20 μs of timing error after 5 hours, respectively. This clearly masks the temperature-induced error of 1.1 μs.

Good oscillator disciplining to minimize frequency errors is critical to achieve low holdover timing errors. Disciplining is the process of synchronizing/syntonizing an oscillator to a superior reference to remove any frequency or phase offset between the two clocks.

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