Microsemi published Version 5 of the RTG4 Datasheet in August 2018 with the following updates:
o Information about RTG4 device status was updated.
o Information about maximum input buffer jitter was added.
o Differential Input signaling waveform diagram was added.
o Information about RAM1K18 – Dual-Port Mode for Depth x Width Configuration 1Kx18 was updated.
o Information about fabric PLL output clock jitter specification was added.
o A footnote about input leakage current of VREF was added.
o Information about FPGA operating limits was updated.
o Information about receiver parameters was updated.
o A footnote about AC transient limit of VDD and VDDI was added.
o Timing diagram of Spacewire characteristics was added.
o Information about tristate leakage current (IOZ) was added.
o Information about combinatorial cell propagation delays was updated.
o Replaced ramp rate with ramp time for DEVRST_N characteristics.
o Information about JTAG AC timing was added.
o DEVRSTN to functional timing waveform diagram was updated.
For questions, please contact Microsemi Programmable Solutions BU marketing team: Ken.O’Neill@microchip.com, Minh.Nguyen@microchip.com, Julian.DiMatteo@microchip.com.
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