Accelerating Positive Change Within the RISC-V Landscape – A Q&A with Microsemi’s Ted Marena

Editor’s Note: A May 2018 announcement by Microsemi of its collaboration with fabless semiconductor company SiFive, aimed at enabling Linux software and firmware developers to build RISC-V PCs, offered the opportunity to ask Ted Marena, director of FPGA/SOC business development at Microsemi, about the significance of the news to the embedded community. Edited excerpts follow.

EECatalog: What are your best arguments for countering the opinion that RISC-V is not yet ready for prime time?

Ted Marena, Microsemi: The momentum behind RISC-V is undeniable. Today the RISC-V Foundation has over 100 member organizations, and it is growing rapidly. Many of the members are tier 1 tech companies. At the most recent RISC-V conference in Barcelona, Spain, NXP, Google, and Western Digital all talked about how they are utilizing RISC-V. RISC-V brings benefits to both the software and hardware technical community. We’re seeing interest in using RISC-V for technologies such as storage controllers, performing management functions, or housekeeping, as embedded controllers on large SoCs, and vector extensions for machine learning.

This Q & A appears on eecatalog.com. Read the full Q&A today.

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