The April 2018 edition of SatNews magazine published an article by Ted Marena and Ken O’Neill from Microsemi that discussed the advantages of using processors based upon the RISC-V open instruction set architecture. The article looks at some of the special challenges space designers have face when deploying processors in space systems, and how the adoption of RISC-V can alleviate those issues. Performance and utilization information is provided for a 32-bit RISC-V implementation in Microsemi’s RTG4 FPGAs. Microsemi has a range of RISC-V IP cores for RTG4 and other FPGAs available todaynow, with more currently in development.
The article can be viewed on SatMagazine.
For more information on RISC-V processor IP or RTG4 FPGAs, connect with me on LinkedIn.
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