RISC-V Meetup: Securing RISC-V Processors and Benefits of a Modifiable Core


Plan to attend the inaugural Rocky Mountain RISC-V Meetup – register here, now.

The meetup will begin with a networking session, followed by presentations and demos. Anyone interested in the RISC-V ISA and related ecosystem is encouraged to attend!


Securing RISC-V Processors – by Dan Ganousis, Dover Microsystems

Benefits of a Modifiable Core – by Keigh Graham, University of Colorado Boulder


July 12, 2018 at 5:30 pm


Sparkfun Electronics, 6333 Dry Creek Parkway, Niwot, CO.


To attend the Meetup, register here.

More Information on RISC-V:

The Mi-V™ RISC-V ecosystem is a continually expanding comprehensive suite of tools and design resources developed by Microsemi and numerous third parties to fully support RISC-V designs. The Mi-V™ ecosystem aims to increase adoption of RISC-V ISA and Microsemi’s soft CPU product family.

There are 6 main categories that make up the Mi-V RISC-V ecosystem: RISC-V soft CPU, design tools, operating systems, solutions, design support, and boards.

More information on the Mi-V embedded ecosystem, partners, news and events.

Follow Microsemi on LinkedIn.

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