With the ever-increasing complexity of algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware so they can catch bugs early in the design cycle. To address this, Microsemi has collaborated with MathWorks® to introduce hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with our FPGA development boards. The new integrated FIL workflow with HDL Coder™ and HDL Verifier™ from MathWorks will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our Libero® SoC Design Suite. Please visit the MathWorks® webpage on Microsemi.com to learn more.
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