PolarFire FPGAs include up to 24 high-speed full-duplex transceiver channels with unique features unavailable in competing devices. The SerDes transceiver was specifically optimized for PolarFire mid-range FPGAs, supporting baud rates from 250 Mbps to 12.7 Gbps, covering the full SDI range of applications. One primary advantage of optimizing for this range over downgrading a higher-speed Serd-Des adapted from a high-end FPGA, is that it has significantly lower power at all baud rates compared to transceivers on competitive mid-range FPGAs.
Exceptionally Low Transceiver Power
The transceivers used in PolarFire FPGAs have the lowest power consumption of any comparable performance transceiver used in any FPGA. The following illustration shows a comparison of the estimated power consumption for several FPGA transceivers at different baud rates.
The figure below represents the power comparison of PolarFire FPGA transceiver to competing SRAM FPGAs.
Transceivers in competitive FPGAs use more than twice the power of PolarFire transceivers and from 3x to 10x more estimated power at most baud rates. Low power consumption is achieved in the PolarFire FPGA transceivers through a unique combination of architectural decisions.
• The transceiver is implemented using a half-rate architecture. High-speed logic is clocked on both edges to keep the high-speed clock networks at half frequency.
• Low transmitter jitter is achieved without the use of high-power logic styles such as CML.
• The transmitter uses an LVDS-style output stage that has good noise immunity and uses less power than other driver types.
• PolarFire FPGAs have the unique ability to shut down the decision feedback equalizer (DFE) and eye monitor when not in use. This is a major power advantage, especially at lower data rates.
• The transmit PLLs use a highly-shared architecture for significant power savings; fewer transmit PLLs used in the device results in lower power
PolarFire FPGAs have 1–6 quad-channel transceivers, for a total of up to 24 SerDes channels, depending upon the family member and device package. To see the exact number of transceivers supported in each device/package combination offered, see the device datasheet. Two secondgeneration PCIe endpoints/root ports are implemented in hardware, supporting a memory mapped AXI4 with built-in DMA (available in every PolarFire FPGA).
The following illustration shows the SerDes features – transceiver architecture and features:
Transceiver Architecture and Features
The PolarFire FPGA transceivers have many special features that enable use with industry-standard protocols in mid-range FPGA applications.
The following equalization features are supported by the PolarFire FPGA.
• The transmit channel has both pre- and post-tap feed-forward equalization (FFE) de-emphasis.
• The receive channel utilizes continuous time linear equalization (CTLE).
• The receive channel has a 5-tap decision-feedback equalizer (DFE).
Together, these features allow longer distances and/or the use of low-cost materials in printed circuit boards and backplanes.
Phase-Locked Loop (PLL) Features
The capabilities and features of the low-power PLL technology used for transmitting PLL and general purpose user-PLLs provides many user benefits.
• Fractional-N architecture, providing flexibility in clock and baud-rate selection.
• Spread-spectrum capability to easily meet maximum radiated emission requirements.
• Removal of transmit jitter up to the top baud rate of 12.7 Gbps, enabling higher bandwidth than competing solutions, and support for Sync-E (1 GbE to 10 GbE).
• Support for unique and independent transmit and receive rates in each transceiver channel.
• Unique CDR PLL capability to support burst mode protocols (such as GPON and XGPON) without the use of oversampling (lower power).
Differentiating Debug and Test
The PolarFire FPGA transceiver has all the expected debug and test features including built-in pseudo-random binary sequence (PRBS) generators and checkers and IEEE 1149.6 “AC JTAG” support for non-DC-coupled signals. Another standard feature is a built-in eye monitor to allow optimal in-situ tuning of FFE and CTLE parameters and problem diagnosis.
The PolarFire FPGA eye monitor can be used in-application to identify the eye margin of the receiver. The following illustration shows the 10.3125 Gbps receive eye measured by on-chip eye monitor with a 26” backplane (FR-4 strip-line) and 7’ line-card (FR-4 micro-strip).
Receiver Eye Diagram:
Measuring the receiver eye diagram improved using FFE, CTLE, and DFE.
The PolarFire FPGA transceivers have the best-in-class implementation for any mid-range FPGA. They have unequaled performance and features at a power consumption point several times lower than the transceivers in competing FPGAs.
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