The ceramic quad flat pack (CQFP) package with 352 pins was recently introduced for RTG4 FPGAs family to provide a more cost-effective… integration than higher pin count packages. The CQFP is the industry-standard package for space applications with well-established board integration and inspection procedures. The first RTG4 CQ352 engineering samples are now available in ES form, which is tested to room temperature, and MS form, which is tested across the full military temperature.
The RTG4 device in the CQ352 package features four embedded SpaceWire clocks and data recovery circuits, and 4 high-speed serialization/deserialization (SERDES) transceivers. This can be used for either native EPCS or PCIE protocols while maintaining the same count of LUTs, flip-flops, DSP math blocks, and SRAM blocks as the existing ceramic column grid array (CCGA) package with 1657 pins. The updated CQ352 pinout is now available here. An update to RTG4 CQ352 pinout is also available in the Libero SoC v11.8 SP1 software tool set, allowing customers to design with the latest package pin assignments. Customers are recommended to download the latest version of the Libero SoC software.
The RTG4 CQ352 samples are available now under the following part numbers: RT4G150-CQ352ES and RT4G150-CQ352MS. The B-flow space flight units are expected to be available in July 2018.
To learn more about the RTG4 device in CQ352 package, please visit the recently-updated RTG4 Product Brief.
For more information on RT FPGAs, please contact me at firstname.lastname@example.org; connect with me on LinkedIn here. I look forward to hearing from you.
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