Understanding Power Supply Rejection Ratio
What is PSRR?
Power Supply Rejection Ratio or Power Supply Ripple Rejection (PSRR) is a measure of how well a circuit rejects noise, of various frequencies, injected at its voltage input. The ripple can be induced from a number of sources, such as a 50Hz/60Hz supply ripple, a switching ripple from a DC/DC converter, or a ripple due to the sharing of an input supply between different circuit blocks on the board. In the timing solutions world, when discussing PSRR we are typically referring to supply ripple.
How does PSRR affect me?
Hardware designers are typically faced with the challenge of increasing the amount of functionality on a PCB while reducing the overall footprint. This often leads to switching to cleaner power supplies at the cost of removing previously necessary filtering circuitry. The often overlooked side-effect is that having multiple components sharing an unfiltered common power supply will propagate any noise and interference generated by one device will now directly impact the jitter performance of all other devices. For platforms where supply ripples were not usually an issue, they now have been introduced to something that can bring an oscillator’s performance to a grinding halt.
For clocking circuits, power supply noise translates into additional jitter. Traditional XOs are very simple circuits composed of an inverting amplifier driving a crystal. Due to their simple design, vendors often overlook evaluating these devices for power supply noise rejection. In many cases, the amplifier is designed, tested and evaluated only in low-noise environments, using a clean power supply and minimal discrete components. Being primarily an analog circuit, sensitive nodes can easily couple noise. That noise will translate to output jitter in the form of spurs that modulate at the fundamental oscillation frequency. The more sensitive the amplifier, the higher the spur magnitude will be for a given amount of noise.
How do I compensate for PSRR?
As a designer, a device’s power supply rejection can typically be managed by applying a filter across the power supply. This can be as simple the addition of a ferrite bead and a discrete SMD capacitor (a low pass filter of sorts). A linear regulator can also be used to filter supply noise (acting as a high pass filter). Depending on what is observed on the power supply, some cases might require having to use both circuits in order to filter across the entire frequency band that a device might experience supply ripple.
As the level of desired performance goes up, the addition of external circuitry can become quite expensive. For this reason many manufacturers of timing devices have begun incorporating circuitry internally in their devices (in the form of LDOs, filters, PLLs, etc.) so as to relieve some of the pressure compensating PSRR can bring. However, as no two systems are the same, design choices made by the timing device manufacturer might not have an impact on the supply ripple observed by the designer! It is also impractical to incorporate an all-encompassing filter circuit on one’s board in case the oscillator happens to perform poorly to specific test conditions. Therefore, we need to develop a test setup in order to evaluate on a case-by-case basis if a device is heavily impacted by PSRR. That’s a blog post for another time.
Tags: Jitter, Oscillator
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