Author: Stephen Bates

Latency Variability

In my last post I talked about the transition to Low-Density Parity-Check (LDPC) Error Correction Codes (ECCs) in enterprise SSD controllers. I hinted that this transition has some interesting implications for the latency of next-generation SSD controllers and I wanted to expand on that topic in this post.

The latency associated with LDPC ECC in SSDs comes from three main sources:

1. The LDPC encoding process.
2. The LDPC decoding associated with the first read of the data on the NAND flash.
3. The LDPC decoding associated with subsequent reads of the data on the NAND flash. Read more »