MAX3612
Low-Jitter Clock Generator with Nine LVDS/LVPECL Outputs
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Overview
The MAX3612 is a high-performance, precision phase-locked loop (PLL) clock generator optimized for next generation high-speed Ethernet applications that demand low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power supply noise rejection, and pin-programmable LVDS/LVPECL output interfaces. The MAX3612 provides nine differential outputs divided into three banks. The frequency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space. This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -40°C to +85°C. |
Applications/Uses
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Key Features
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Resources
Datasheet | MAX3612 Data Sheet |
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Evaluation Kits | MAX3612 Evaluation Kit Data Sheet |
Reliability Reports | MAX3612 Reliability Report |
Models | MAX3612 IBIS Model |
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