Microsemi Delivers the Lowest Power FPGAs
SmartFusion2 SoC FPGAs and IGLOO2 FPGAs have dramatically lower static power than competitive FPGAs. This is enabled by the inherent low leakage of Microsemi’s Flash based FPGA architecture. In addition, SmartFusion2 and IGLOO2 Flash Freeze capability enables even lower power operation for low duty cycle applications.
The SmartFusion2 and IGLOO2 families include important low power features:
- No In Rush and Configuration Current
- Industry’s lowest power 5G SERDES
- Industry’s lowest static power
- Flash Freeze real time low power state
- ARM Cortex M3 low power modes
- SoC peripheral low power modes
Watch Video Now: To view details of the competitive power comparisons and a demonstration of power analysis with IGLOO2 devices please watch the Low Power webinar recording.
No In Rush and Configuration Current
SRAM FPGAs power up in an unconfigured state and needs to complete the initial power-up and reset sequence. Initially, the various configuration bits are in unknown states and need to initialize on every power cycle. Hence, a current surge is created that may generate a spike as high as several amperes for as long as a few hundred microseconds resulting in an In-rush power.
To mitigate this current spike, many SRAM FPGAs have added complex power sequencing requirements to the system.
As Microsemi FPGA are non-volatile and do not need external configuration devices for reprogrammability, Microsemi Flash FPGA eliminates hundreds of milliwatts at device startup and the need for external devices mitigation.
Industry’s Lowest Static Power
Unlike SRAM cells used in competitors FPGAs, which are typically built using six transistors, our Flash based cells are built using a single transistor, translating into exponentially lower leakage current versus SRAM cells.
Minimizing Dynamic Power Consumption
Customers can enjoy lower dynamic power with SmartFusion2 and Igloo2 through:
- Best in class 5G transceiver power: power per Gbps for each SERDES lane is as low as 13mW, which is upto 5X lower when compared to other cost optimized FPGAs with similar capabilities
- More hard IP and resources in smaller devices (link to TCO page): Igloo2 and SmartFusion2 provide more I/O, more transceivers, more PCI Express Endpoints and a unique high performance memory subsystem (link to HPMS page) to provide more capabilities in smaller and low power devices
- Unlike our competitors, Mirosemi has chosen to embed a processor subsystem that has inherently lower power. The embedded Cortex M3 subsystem (link to MSS page if we have one) has multiple low power modes including a Sleep Mode and a Deep Sleep mode
- We also provide ways for the user to optimize designs for lower power using various tools to compute power profiles, smart floorplanning and power optimized place and route. Details are provided in AC323 (link to doc)
Power Comparison for FPGAs
Power Comparison for SoC FPGAs
SERDES Power Comparison
Microsemi devices offer Industry’s lowest power 5G SerDes with power as low as 13mW/Gbps/Lane only.
FlashFreeze ModeIn systems that operate reactively or periodically, SmartFusion2 and IGLOO2 can dramatically reduce power. Saving energy in periodic and reactive systems is achieved by moving into a very low power state when processing is not necessary. This is possible within SmartFusion2 using the ARM Cortex M3 low power modes and Flash-Freeze low power more for the FPGA fabric and IOs. The capabilities of Flash Freeze are completely unique in FPGAs.
Figure 1: Example system moving from Flash Freeze to Regular Operation and back to Flash Freeze
Flash Freeze enables the rapid stopping and starting of the FPGA fabric and related IOs while preserving the state of the FPGA fabric and dramatically reducing power. The time to enter Flash Freeze is approximately 100 usec and the time to exit Flash Freeze is also about 100 usec. While in Flash Freeze, the state of the FPGA is maintained so that upon exit from Flash Freeze, the device continues to operate from where it left off.
Triggering Flash Freeze Exit
Exiting Flash Freeze can be initiated through IO or through the ARM Cortex-M3. These methods send a message to the system controller to begin Flash Freeze exit.
Using IO to trigger Flash Freeze exit can be done either with "Signature Mode" or "Activity Mode" settings. In "Signature Mode", a selected set of IOs are configured as inputs with predetermined 1 and 0 comparison states. When the input signals for all the "Signature Mode" IOs match their predetermined 1 and 0 states, the system will initiate Flash Freeze exit. All IOs in "Signature Mode" are compared as a single signature. In "Activity Mode", a selected set of IOs are configured as inputs and any change on any of the inputs will initiate Flash Freeze exit. The device can be also have a combination of one group of "Signature Mode" inputs and a set of "Activity Mode" inputs, either of which can initiate Flash Freeze exit.
The ARM Cortex M3 can initiate a Flash Freeze exit through a communication to the system controller through the comm port.
Initiating Flash Freeze Entry
Flash Freeze low-power mode can be initiated from the ARM Cortex M3, the IO or from a core logic signal in the FPGA fabric. This flexibility includes all the capabilities for exiting Flash Freeze, but also adds the FPGA fabric as an additional method. Using the FPGA fabric, nearly any desired complex event or state can initiate the Flash Freeze low power mode.
Applications of Flash Freeze
In low power communication systems, power is reduced by using periodic bursts of communication. This eliminates the constant power in the amplifiers and the rest of the system.
- Sensor Networks
Sensor networks include both low power communications and active sensors to perform distributed measurements. The active sensors may be turned on periodically (Traffic image, weather sensor) or turn on in response to an event (Earthquake). After the measurement has been taken, the information is uploaded as an information burst and then the equipment goes back to sleep – Flash Freeze.
- Medical Equipment
Many types of medical equipment is used for monitoring patient health. These types of systems have relatively low sampling rates and can therefore utilize periodic operation as a means to minimize power consumption. This is especially useful in portable medical equipment.
Low Power Resources
|Industrys Lowest Power FPGAs Fact Sheet||143 KB||10/2008|
|Power Top Ten||173 KB||10/2008|
|Total System Power Brochure||482 KB||10/2008|
|SmartFusion2 Lowest Power FPGAs White Paper||10/2012|
|Mixed Signal Power Management White Paper||6/2010|
|Power-Aware FPGA Design White Paper||1 MB||2/2009|
|High-Volume nano FPGAs White Paper||415 KB||11/2008|
|Competitive Programmable Logic Power Comparison White Paper||1 MB||4/2008|
|The Many Flavors of Low-Power, Low-Cost FPGAs White Paper||517 KB||4/2008|
|The New "Power-Smart" Power Paradigm White Paper||210 KB||7/2007|
|Reducing System Power White Paper||33 KB||8/2006|
|AC323: Dynamic Power Reduction in Flash FPGAs App Note||2 MB||10/2012|
|HB: Microsemi's Flash*Freeze and Low-Power Modes (v2.3)||872 KB||11/2009|
|HB: Low-Power Modes in Microsemi ProASIC3/E FPGAs (v1.2)||432 KB||8/2009|
|AC143: Power Conscious Design with ProASIC App Note||550 KB||11/2000|
|AC140: Design for Low Power in Microsemi Antifuse FPGAs App Note||155 KB||9/2000|
|AC138: Power Requirements: Microsemi A54SX08 vs. Altera CPLDs App Note||75 KB||4/2000|
|AC109: Predicting the Power Dissipation of Microsemi FPGAs App Note||67 KB||4/1996|
|AC400: SmartFusion2 Flash*Freeze Entry and Exit - With SoftConsole - Libero SoC v11.4||1.54 MB||9/2014|
|AC290: Trainable Image Recognition System Using Low Power Flash FPGAs App Brief||167 KB||11/2006|
|AC259: Lower Power Operation with the Fusion Device App Brief||57 KB||6/2006|
|AC258: Context Save and Reload with Real-Timestamp App Brief||51 KB||6/2006|
|IGLOO Power Calculator
(applicable to IGLOO, IGLOOe, and IGLOO nano)
|ProASIC3 Power Calculator
(applicable to ProASIC3, ProASIC3E, ProASIC3 nano, ProASIC3L, and RT ProASIC3)
|SmartFusion Power Calculator||648 KB||9/2011|
|Fusion Power Calculator||800 KB||1/2012|
|AX and RTAX-S/SL/D Power Calculator||436 KB||1/2011|
|ProASICPLUS Power Calculator||38 KB||12/2004|
|eX, SX-A and RT54SX-S Power Calculator||853 KB||2/2012|
|ProASIC Power Calculator||35 KB||3/2003|
|Power FAQs||49 KB||8/2006|