Design Entry and Implementation
Overview
System Builder is an easy-to-use design tool that walks users through a set of high-level questions that will define your intended system. System Builder design tool for ARM®-based SoC design now offers an improved graphical interface with a broader range of integrated blocks and IP allowing fast and reliable automated system configuration and assembly
Enhancing Ease-of-Use
- Asks basic questions about your system architecture
- Adds any additional needed peripherals in the fabric
- Builds a correct-by-design complete system
Expanding Configuration
- The built-in design rule check feature prevents you from moving forward if there are mistakes or conflicts.
- You can also extend the System Builder generated design with your own custom peripherals and logic by specifying your options and then using SmartDesign to connect up your custom peripherals.
- Sets required configuration options for each selected feature
- DDR Configuration Tool eliminates the need to understand low level registers
- DDR Configuration files for most popular memories provided
Expediting Implementation
- The design that is produced by the System Builder follows all the SmartFusion2 silicon design rules.
- Eight step design flow to generate a configured system with
- Clock components, Configuration IP, Fabric slaves and Bus Interfaces
- Enables you to focus on your design specializations instead of on the specific silicon requirements of a SmartFusion2 or IGLOO2 based design
SmartDesign
SmartDesign
Conventional design approaches use schematic and HDL code generation. While designing at this level is a well-seasoned design practice used by many, significant time and effort (much of it very tedious) can be saved if the designer could visualize and construct designs at a higher level and automatically generate a single functional HDL file that is synthesis ready. SmartDesign is the Microsemi solution.
SmartDesign uses a block diagram approach for the visualization, instantiation and connection of the design using the full range of design objects: User Created, 3rd Party Created, and Catalog Cores. The user, under program guidance, easily adds, and configures objects in the design ‘canvas’. Connections are made either automatically or manually via a simple point-and-click approach. The final result is a design-rule-checked and automatically abstracted synthesis-ready HDL file. The output can then be used by the standard Libero flow, all the way from Synthesis to Device programming.
Key Features List
- Visual block-based design creation tool
- Assemble and connect Microsemi IP, user-generated IP, custom/glue-logic HDL modules
- All construction performed within a single canvas view
- All ports exposed on the canvas, available for connection
- Automatic connections to compatible peripherals and busses
- Point-and-click manual connections
- Guidance to compatible interfaces and required peripherals
- Dynamic error check, continuous file audit
- Automatic generation of test bench for clock and resets
- Bus functional model (BFM) generation for processor designs
- Datasheet report
- View the entire SmartDesign as a system, with all interconnects
- Automatic abstraction to synthesis-ready HDL: Verilog or VHDL
- Efficient construction of complex or simple designs, including bus-based designs with processor and SmartFusion or Fusion mixed signal FPGAs
- Complete FPGA SoC, FPGA subsystem, or embedded SmartDesign-in-SmartDesign
- Supported in Libero Standalone (SA) licenses