Project Settings
Project Name Core_SDLC_syn Implementation Name synthesis
Top Module Core_SDLC Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
Compile InputComplete 46 118 0 - 0m:03s - 4/8/2015
12:05:15 PM
Pre-mappingComplete 88 2 0 0m:00s 0m:04s 137MB 4/8/2015
12:05:22 PM
Map & OptimizeComplete 32 14 0 0m:05s 0m:11s 195MB 4/8/2015
12:05:34 PM

Area Summary
Carry Cells 34 Sequential Cells 657
DSP Blocks (MACC) (dsp_used) 0 I/O Cells 14
Global Clock Buffers 3 Block Rams (RAM1K18) (v_ram) 4
LUTs (total_luts) 1091

Timing Summary
Clock NameReq FreqEst FreqSlack
Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock100.0 MHz96.3 MHz-0.384
System100.0 MHz401.4 MHz7.509

Optimizations Summary
Combined Clock Conversion 1 / 0