#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014
#install: \\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1
#OS: Windows 7 6.1
#Hostname: W764-KHADGIS1

#Implementation: synthesis

$ Start of Compile
#Wed Apr 08 12:05:12 2015

Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1\lib\generic\smartfusion2.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1\lib\vlog\umr_capim.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1\lib\vlog\scemi_objects.v"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1\lib\vlog\scemi_pipes.svh"
@I::"\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1\lib\vlog\hypermods.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC_sb\CCC_0\Core_SDLC_sb_CCC_0_FCCC.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC_sb_MSS\Core_SDLC_sb_MSS_syn.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC_sb_MSS\Core_SDLC_sb_MSS.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\SgCore\OSC\1.0.103\osc_comps.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC_sb\FABOSC_0\Core_SDLC_sb_FABOSC_0_OSC.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CoreAPB3\4.1.5\rtl\vlog\core\coreapb3_muxptob3.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CoreAPB3\4.1.5\rtl\vlog\core\coreapb3_iaddr_reg.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CoreAPB3\4.1.5\rtl\vlog\core\coreapb3.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC_sb\Core_SDLC_sb.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC\FCCC_0\Core_SDLC_FCCC_0_FCCC.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_sfr.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_fifo.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_crc.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_receive.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_transmit.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_main.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc_dualram.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\Actel\DirectCore\CORESDLC\3.0.121\rtl\vlog\core\coresdlc.v"
@I::"D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\component\work\Core_SDLC\Core_SDLC.v"
@W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
@W:CG775 : coresdlc.v(29) | Found Component CORESDLC in library CORESDLC_LIB
@W:CG775 : coresdlc.v(29) | Found Component CORESDLC in library CORESDLC_LIB
Verilog syntax check successful!
Selecting top level module Core_SDLC
@N:CG364 : smartfusion2.v(371) | Synthesizing module VCC

@N:CG364 : smartfusion2.v(367) | Synthesizing module GND

@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

@N:CG364 : smartfusion2.v(722) | Synthesizing module CCC

@N:CG364 : Core_SDLC_sb_CCC_0_FCCC.v(5) | Synthesizing module Core_SDLC_sb_CCC_0_FCCC

@N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

@N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

@N:CG364 : Core_SDLC_sb_MSS_syn.v(5) | Synthesizing module MSS_075

@N:CG364 : Core_SDLC_sb_MSS.v(9) | Synthesizing module Core_SDLC_sb_MSS

@W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3

@N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	IADDR_OPTION=32'b00000000000000000000000000000000
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b1
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	SC_0=1'b0
	SC_1=1'b0
	SC_2=1'b0
	SC_3=1'b0
	SC_4=1'b0
	SC_5=1'b0
	SC_6=1'b0
	SC_7=1'b0
	SC_8=1'b0
	SC_9=1'b0
	SC_10=1'b0
	SC_11=1'b0
	SC_12=1'b0
	SC_13=1'b0
	SC_14=1'b0
	SC_15=1'b0
	MADDR_BITS=6'b010000
	UPR_NIBBLE_POSN=4'b0011
	FAMILY=32'b00000000000000000000000000010011
	SYNC_RESET=32'b00000000000000000000000000000000
	IADDR_NOTINUSE=32'b00000000000000000000000000000000
	IADDR_EXTERNAL=32'b00000000000000000000000000000001
	IADDR_SLOT0=32'b00000000000000000000000000000010
	IADDR_SLOT1=32'b00000000000000000000000000000011
	IADDR_SLOT2=32'b00000000000000000000000000000100
	IADDR_SLOT3=32'b00000000000000000000000000000101
	IADDR_SLOT4=32'b00000000000000000000000000000110
	IADDR_SLOT5=32'b00000000000000000000000000000111
	IADDR_SLOT6=32'b00000000000000000000000000001000
	IADDR_SLOT7=32'b00000000000000000000000000001001
	IADDR_SLOT8=32'b00000000000000000000000000001010
	IADDR_SLOT9=32'b00000000000000000000000000001011
	IADDR_SLOT10=32'b00000000000000000000000000001100
	IADDR_SLOT11=32'b00000000000000000000000000001101
	IADDR_SLOT12=32'b00000000000000000000000000001110
	IADDR_SLOT13=32'b00000000000000000000000000001111
	IADDR_SLOT14=32'b00000000000000000000000000010000
	IADDR_SLOT15=32'b00000000000000000000000000010001
	SL0=16'b0000000000000001
	SL1=16'b0000000000000010
	SL2=16'b0000000000000000
	SL3=16'b0000000000000000
	SL4=16'b0000000000000000
	SL5=16'b0000000000000000
	SL6=16'b0000000000000000
	SL7=16'b0000000000000000
	SL8=16'b0000000000000000
	SL9=16'b0000000000000000
	SL10=16'b0000000000000000
	SL11=16'b0000000000000000
	SL12=16'b0000000000000000
	SL13=16'b0000000000000000
	SL14=16'b0000000000000000
	SL15=16'b0000000000000000
	SC=16'b0000000000000000
	SC_qual=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@W:CG360 : coreapb3.v(244) | No assignment to wire IA_PRDATA

@N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000000
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000000
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	SDIF0_PCIE=32'b00000000000000000000000000000000
	SDIF1_PCIE=32'b00000000000000000000000000000000
	SDIF2_PCIE=32'b00000000000000000000000000000000
	SDIF3_PCIE=32'b00000000000000000000000000000000
	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
	DEVICE_090=32'b00000000000000000000000000000001
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	SDIF_INTERVAL=32'b00000000000000000001100101100100
	DDR_INTERVAL=32'b00000000000000000010011100010000
	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreResetP_Z2

@W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] 

@W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] 

@W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] 

@W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] 

@W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 

@W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc 

@W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable 

@W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable 

@W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable 

@W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable 

@W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable 

@N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
@W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset 

@W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int 

@W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] 

@W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 

@W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base 

@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

@N:CG364 : Core_SDLC_sb_FABOSC_0_OSC.v(5) | Synthesizing module Core_SDLC_sb_FABOSC_0_OSC

@N:CG364 : smartfusion2.v(713) | Synthesizing module SYSRESET

@N:CG364 : Core_SDLC_sb.v(9) | Synthesizing module Core_SDLC_sb

@W:CG775 : coresdlc.v(29) | Found Component CORESDLC in library CORESDLC_LIB
@N:CG364 : coresdlc_sfr.v(29) | Synthesizing module CORESDLC_SFR

@N:CG364 : coresdlc_fifo.v(30) | Synthesizing module CORESDLC_FIFO

@N:CG364 : coresdlc_crc.v(29) | Synthesizing module CORESDLC_CRC

@N:CG364 : coresdlc_receive.v(30) | Synthesizing module CORESDLC_RECEIVE

@N:CG364 : coresdlc_transmit.v(30) | Synthesizing module CORESDLC_TRANSMIT

@N:CG364 : coresdlc_main.v(31) | Synthesizing module CORESDLC_MAIN

@N:CG364 : coresdlc_dualram.v(32) | Synthesizing module CORESDLC_DUALRAM

@N:CG364 : coresdlc.v(29) | Synthesizing module CORESDLC

@W:CG775 : coresdlc.v(29) | Found Component CORESDLC in library CORESDLC_LIB
@N:CG364 : Core_SDLC_FCCC_0_FCCC.v(5) | Synthesizing module Core_SDLC_FCCC_0_FCCC

@N:CG364 : Core_SDLC.v(9) | Synthesizing module Core_SDLC

@N:CL134 : coresdlc_dualram.v(49) | Found RAM store, depth=3, width=8
@N:CL201 : coresdlc_transmit.v(260) | Trying to extract state machine for register sm
Extracted state machine for register sm
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL247 : coresdlc_transmit.v(40) | Input port bit 0 of ifsreg[7:0] is unused

@N:CL201 : coresdlc_receive.v(840) | Trying to extract state machine for register csm
Extracted state machine for register csm
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@N:CL201 : coresdlc_receive.v(226) | Trying to extract state machine for register sm
Extracted state machine for register sm
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@W:CL157 : Core_SDLC_sb_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : Core_SDLC_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : Core_SDLC_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W:CL157 : Core_SDLC_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : Core_SDLC_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W:CL159 : Core_SDLC_sb_FABOSC_0_OSC.v(14) | Input XTL is unused
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
@N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
@N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
Extracted state machine for register sdif3_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
Extracted state machine for register sdif2_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
Extracted state machine for register sdif1_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
Extracted state machine for register sdif0_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused
@W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
@W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
@W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused
@W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused
@W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused
@W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
@W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
@W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
@W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
@W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
@W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
@W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
@W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
@W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
@W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused
@W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused
@W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused
@W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused
@W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused
@W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused
@W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused
@W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused
@W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused
@W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused
@W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused
@W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused
@W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused
@W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused
@W:CL159 : coreapb3.v(72) | Input IADDR is unused
@W:CL159 : coreapb3.v(73) | Input PRESETN is unused
@W:CL159 : coreapb3.v(74) | Input PCLK is unused
@W:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused
@W:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused
@W:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused
@W:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused
@W:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused
@W:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused
@W:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused
@W:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused
@W:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused
@W:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused
@W:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused
@W:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused
@W:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused
@W:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused
@W:CL159 : coreapb3.v(123) | Input PREADYS2 is unused
@W:CL159 : coreapb3.v(124) | Input PREADYS3 is unused
@W:CL159 : coreapb3.v(125) | Input PREADYS4 is unused
@W:CL159 : coreapb3.v(126) | Input PREADYS5 is unused
@W:CL159 : coreapb3.v(127) | Input PREADYS6 is unused
@W:CL159 : coreapb3.v(128) | Input PREADYS7 is unused
@W:CL159 : coreapb3.v(129) | Input PREADYS8 is unused
@W:CL159 : coreapb3.v(130) | Input PREADYS9 is unused
@W:CL159 : coreapb3.v(131) | Input PREADYS10 is unused
@W:CL159 : coreapb3.v(132) | Input PREADYS11 is unused
@W:CL159 : coreapb3.v(133) | Input PREADYS12 is unused
@W:CL159 : coreapb3.v(134) | Input PREADYS13 is unused
@W:CL159 : coreapb3.v(135) | Input PREADYS14 is unused
@W:CL159 : coreapb3.v(136) | Input PREADYS15 is unused
@W:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused
@W:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused
@W:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused
@W:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused
@W:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused
@W:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused
@W:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused
@W:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused
@W:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused
@W:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused
@W:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused
@W:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused
@W:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused
@W:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused
@END

At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 80MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Apr 08 12:05:15 2015

###########################################################]
Pre-mapping Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Linked File: Core_SDLC_scck.rpt
Printing clock  summary report in "D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\synthesis\Core_SDLC_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 106MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 106MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB)

@W:BN132 : coreresetp.v(1089) | Removing sequential instance Core_SDLC_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance Core_SDLC_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_crc.v(115) | Removing sequential instance datao of view:PrimLib.dffr(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_CRC_u_crc_u_crc(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_crc.v(133) | Removing sequential instance match of view:PrimLib.dffs(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_CRC_u_crc_0_u_crc(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_crc.v(115) | Removing sequential instance datao of view:PrimLib.dffr(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_CRC_u_crc_u_crc_0(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_crc.v(133) | Removing sequential instance match of view:PrimLib.dffs(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_CRC_u_crc_0_u_crc_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance INIT_DONE_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1089) | Removing sequential instance sm0_state[6:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_transmit.v(487) | Removing sequential instance den of view:PrimLib.dffse(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_TRANSMIT_u_transmit(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_sfr.v(361) | Removing sequential instance re of view:PrimLib.dffr(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_SFR_u_sfr(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_sfr.v(343) | Removing sequential instance rv of view:PrimLib.dffr(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_SFR_u_sfr(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_transmit.v(487) | Removing sequential instance den of view:PrimLib.dffse(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_TRANSMIT_u_transmit_0(verilog) because there are no references to its outputs 
@N:BN362 : coresdlc_sfr.v(325) | Removing sequential instance tv of view:PrimLib.dffr(prim) in hierarchy view:CORESDLC_LIB.CORESDLC_SFR_u_sfr_0(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(946) | Removing sequential instance CONFIG2_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(963) | Removing sequential instance sdif3_spll_lock_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(929) | Removing sequential instance CONFIG1_DONE_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif3_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif2_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif1_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance release_sdif0_core_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1646) | Removing sequential instance ddr_settled_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1581) | Removing sequential instance release_sdif3_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1549) | Removing sequential instance release_sdif2_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1517) | Removing sequential instance release_sdif1_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1485) | Removing sequential instance release_sdif0_core of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(1613) | Removing sequential instance ddr_settled of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(755) | Removing sequential instance sm0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(912) | Removing sequential instance sdif3_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(898) | Removing sequential instance sdif2_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(884) | Removing sequential instance sdif1_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(870) | Removing sequential instance sdif0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(856) | Removing sequential instance sm0_areset_n_rcosc_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN115 : core_sdlc_sb.v(546) | Removing instance FABOSC_0 of view:work.Core_SDLC_sb_FABOSC_0_OSC(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_re of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q3 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q2 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(733) | Removing sequential instance SDIF3_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(714) | Removing sequential instance SDIF2_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(695) | Removing sequential instance SDIF1_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
@N:BN362 : coreresetp.v(676) | Removing sequential instance SDIF0_PERST_N_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs 
syn_allowed_resources : blockrams=109  set on top level netlist Core_SDLC


Clock Summary
**************

Start                                              Requested     Requested     Clock        Clock              
Clock                                              Frequency     Period        Type         Group              
---------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0
System                                             1.0 MHz       1000.000      system       system_clkgroup    
===============================================================================================================

@W:MT530 : core_sdlc_sb_mss.v(274) | Found inferred clock Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 717 sequential elements including Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 

Finished Pre Mapping Phase.
@N:BN225 :  | Writing default property annotation file D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\synthesis\Core_SDLC.sap. 
Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 137MB)

Process took 0h:00m:04s realtime, 0h:00m:01s cputime
# Wed Apr 08 12:05:22 2015

###########################################################]
Map & Optimize Report

Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2013.09M-SP1 

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

@W:MO171 : coresdlc_receive.v(970) | Sequential instance CORESDLC_1.u_sdlc.u_receive.rxc_ff reduced to a combinational gate by constant propagation 
@W:MO171 : coresdlc_transmit.v(689) | Sequential instance CORESDLC_0.u_sdlc.u_transmit.txc_ff reduced to a combinational gate by constant propagation 
@W:MO171 : coresdlc_transmit.v(689) | Sequential instance CORESDLC_1.u_sdlc.u_transmit.txc_ff reduced to a combinational gate by constant propagation 
@W:BN132 : coresdlc_receive.v(983) | Removing sequential instance CORESDLC_1.u_sdlc.u_receive.rce_ff,  because it is equivalent to instance CORESDLC_1.u_sdlc.u_receive.rce

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

@N:MF135 : coresdlc_dualram.v(49) | Found RAM 'u_rx_ram.store[7:0]', 4 words by 8 bits 
@N:MF135 : coresdlc_dualram.v(49) | Found RAM 'u_tx_ram.store[7:0]', 4 words by 8 bits 
@N:FX403 : coresdlc_dualram.v(49) | Property "block_ram" or "no_rw_check" found for RAM u_rx_ram.store[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : coresdlc_dualram.v(49) | No read/write conflict check. Possible simulation mismatch!
@N:MF707 : coresdlc_dualram.v(49) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for u_rx_ram.store[7:0] (view:CORESDLC_LIB.CORESDLC_CORESDLC_0(verilog)).
@N:FX403 : coresdlc_dualram.v(49) | Property "block_ram" or "no_rw_check" found for RAM u_tx_ram.store[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : coresdlc_dualram.v(49) | No read/write conflict check. Possible simulation mismatch!
@N:MF707 : coresdlc_dualram.v(49) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for u_tx_ram.store[7:0] (view:CORESDLC_LIB.CORESDLC_CORESDLC_0(verilog)).
@W:BN132 : coresdlc_dualram.v(69) | Removing sequential instance CORESDLC_0.u_tx_ram.rdata_int_rst,  because it is equivalent to instance CORESDLC_0.u_rx_ram.rdata_int_rst
@N:BN362 : coresdlc_sfr.v(166) | Removing sequential instance ifsreg[0] in hierarchy view:CORESDLC_LIB.CORESDLC_SFR_u_sfr(verilog) because there are no references to its outputs 
@N: : coresdlc_sfr.v(380) | Found counter in view:CORESDLC_LIB.CORESDLC_SFR_u_sfr(verilog) inst baud_count[7:0]
Encoding state machine csm[4:0] (view:CORESDLC_LIB.CORESDLC_RECEIVE(verilog))
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine sm[3:0] (view:CORESDLC_LIB.CORESDLC_RECEIVE(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   011 -> 11
Encoding state machine sm[6:0] (view:CORESDLC_LIB.CORESDLC_TRANSMIT(verilog))
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
@N:FX404 : coresdlc_transmit.v(593) | Found addmux in view:CORESDLC_LIB.CORESDLC_TRANSMIT(verilog) inst ifs_count_13[8:1] from un1_ifs_count_1[7:0] 
@N:MF135 : coresdlc_dualram.v(49) | Found RAM 'u_rx_ram.store[7:0]', 4 words by 8 bits 
@N:MF135 : coresdlc_dualram.v(49) | Found RAM 'u_tx_ram.store[7:0]', 4 words by 8 bits 
@N:FX403 : coresdlc_dualram.v(49) | Property "block_ram" or "no_rw_check" found for RAM u_rx_ram.store[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : coresdlc_dualram.v(49) | No read/write conflict check. Possible simulation mismatch!
@N:MF707 : coresdlc_dualram.v(49) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for u_rx_ram.store[7:0] (view:CORESDLC_LIB.CORESDLC_CORESDLC_1(verilog)).
@N:FX403 : coresdlc_dualram.v(49) | Property "block_ram" or "no_rw_check" found for RAM u_tx_ram.store[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : coresdlc_dualram.v(49) | No read/write conflict check. Possible simulation mismatch!
@N:MF707 : coresdlc_dualram.v(49) | Insert external logic with either syn_ramstyle=rw_check attribute or enable 'Read Write Check on RAM' option to resolve read/write conflict for u_tx_ram.store[7:0] (view:CORESDLC_LIB.CORESDLC_CORESDLC_1(verilog)).
@W:BN132 : coresdlc_dualram.v(69) | Removing sequential instance CORESDLC_1.u_tx_ram.rdata_int_rst,  because it is equivalent to instance CORESDLC_1.u_rx_ram.rdata_int_rst
@N:BN362 : coresdlc_sfr.v(166) | Removing sequential instance ifsreg[0] in hierarchy view:CORESDLC_LIB.CORESDLC_SFR_u_sfr_0(verilog) because there are no references to its outputs 
@N: : coresdlc_sfr.v(380) | Found counter in view:CORESDLC_LIB.CORESDLC_SFR_u_sfr_0(verilog) inst baud_count[7:0]
Encoding state machine csm[4:0] (view:CORESDLC_LIB.CORESDLC_RECEIVE_u_receive(verilog))
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
Encoding state machine sm[3:0] (view:CORESDLC_LIB.CORESDLC_RECEIVE_u_receive(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   011 -> 11
@W:BN132 : coresdlc_dualram.v(69) | Removing instance CORESDLC_1.u_rx_ram.rdata_int_rst,  because it is equivalent to instance CORESDLC_0.u_rx_ram.rdata_int_rst

Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 152MB peak: 153MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 148MB peak: 153MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 153MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 153MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 153MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 153MB)


Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:02s; Memory used current: 146MB peak: 153MB)


Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 195MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -3.49ns		1090 /       653
------------------------------------------------------------

@N:FX271 : coresdlc_transmit.v(260) | Instance "CORESDLC_1.u_sdlc.u_transmit.sm[0]" with 7 loads replicated 1 times to improve timing 
@N:FX271 : coresdlc_transmit.v(584) | Instance "CORESDLC_0.u_sdlc.u_transmit.ifs_num" with 4 loads replicated 1 times to improve timing 
@N:FX271 : coresdlc_transmit.v(584) | Instance "CORESDLC_0.u_sdlc.u_transmit.ifs_count[1]" with 4 loads replicated 1 times to improve timing 
@N:FX271 : coresdlc_transmit.v(584) | Instance "CORESDLC_1.u_sdlc.u_transmit.ifs_count[6]" with 5 loads replicated 1 times to improve timing 
Timing driven replication report
Added 4 Registers via timing driven replication
Added 2 LUTs via timing driven replication



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -2.67ns		1097 /       657
------------------------------------------------------------



Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -2.67ns		1097 /       657
------------------------------------------------------------

@N:BN362 :  | Removing sequential instance CORESDLC_1.u_tx_ram.store_store_0_0_en in hierarchy view:work.Core_SDLC(verilog) because there are no references to its outputs  
@N:BN362 :  | Removing sequential instance CORESDLC_1.u_rx_ram.store_store_0_0_en in hierarchy view:work.Core_SDLC(verilog) because there are no references to its outputs  
@N:BN362 :  | Removing sequential instance CORESDLC_0.u_tx_ram.store_store_0_0_en in hierarchy view:work.Core_SDLC(verilog) because there are no references to its outputs  
@N:BN362 :  | Removing sequential instance CORESDLC_0.u_rx_ram.store_store_0_0_en in hierarchy view:work.Core_SDLC(verilog) because there are no references to its outputs  
@N:FP130 :  | Promoting Net Core_SDLC_sb_0_MSS_READY on CLKINT  I_197  

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 195MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 195MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 666 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

================================================== Non-Gated/Non-Generated Clocks ==================================================
Clock Tree ID     Driving Element                   Drive Element Type     Fanout     Sample Instance                               
------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        Core_SDLC_sb_0.CCC_0.GL0_INST     CLKINT                 666        Core_SDLC_sb_0.CORERESETP_0.MSS_HPMS_READY_int
====================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]

Writing Analyst data base D:\SVN\CoreSDLC\trunk\current\test\test_design\CoreSDLC_Test_Design_SmartFusion2\Core_SDLC\synthesis\Core_SDLC.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:04s; Memory used current: 154MB peak: 195MB)

Writing EDIF Netlist and constraint files
@N:BW103 :  | Synopsys Constraint File time units using default value of 1ns  
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  
I-2013.09M-SP1 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:05s; Memory used current: 155MB peak: 195MB)

@W:MT246 : core_sdlc_fccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : core_sdlc_sb.v(559) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT420 :  | Found inferred clock Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Core_SDLC_sb_0.CCC_0.GL0_net" 



##### START OF TIMING REPORT #####[
# Timing Report written on Wed Apr 08 12:05:34 2015
#


Top view:               Core_SDLC
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary 
*******************


Worst slack in design: -0.384

                                                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock                                     Frequency     Frequency     Period        Period        Slack      Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     100.0 MHz     96.3 MHz      10.000        10.384        -0.384     inferred     Inferred_clkgroup_0
System                                             100.0 MHz     401.4 MHz     10.000        2.491         7.509      system       system_clkgroup    
======================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                        Ending                                          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                          System                                          |  10.000      7.509   |  No paths    -      |  No paths    -      |  No paths    -    
System                                          Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      8.526   |  No paths    -      |  No paths    -      |  No paths    -    
Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock  System                                          |  10.000      2.078   |  No paths    -      |  No paths    -      |  No paths    -    
Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock  Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      -0.384  |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                                                     Starting                                                                                                                                Arrival           
Instance                                             Reference                                          Type        Pin                Net                                                   Time        Slack 
                                                     Clock                                                                                                                                                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[3]      Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[3]                  3.035       -0.384
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[4]      Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[4]                  3.187       -0.319
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[2]      Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[2]                  3.014       -0.262
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[1]      Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[1]                  3.038       -0.253
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[0]      Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[0]                  3.056       -0.204
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_SEL          Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PSELx         3.083       0.148 
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[14]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[14]     3.012       0.162 
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[13]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[13]     3.017       0.268 
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[5]      Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[5]                  3.021       0.443 
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[12]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[12]     3.046       0.933 
===============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                     Starting                                                                                                                                Required           
Instance                                             Reference                                          Type        Pin                Net                                                   Time         Slack 
                                                     Clock                                                                                                                                                      
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[3]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]     9.074        -0.384
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[2]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]     8.732        -0.319
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[4]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]     9.039        -0.087
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[1]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]     9.014        -0.044
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[7]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[7]     9.029        -0.022
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[6]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]     9.082        0.031 
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[0]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]     9.065        0.074 
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST     Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[5]     Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]     9.053        0.394 
CORESDLC_0.u_sdlc.u_transmit.u_fifo.ifull            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                 un12_ifull_c_i_0                                      9.707        1.279 
CORESDLC_1.u_sdlc.u_receive.rcabt                    Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE         EN                 N_21                                                  9.707        1.384 
================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.926
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.074

    - Propagation time:                      9.458
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.384

    Number of logic level(s):                7
    Starting point:                          Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[3]
    Ending point:                            Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                          Pin                Pin               Arrival     No. of    
Name                                                        Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_ADDR[3]      Out     3.035     3.035       -         
Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[3]                        Net         -                  -       1.005     -           99        
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am_1_1[3]               CFG4        D                  In      -         4.040       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am_1_1[3]               CFG4        Y                  Out     0.411     4.451       -         
sfrdatao_12_am_1_1[3]                                       Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am[3]                   CFG4        D                  In      -         4.934       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am[3]                   CFG4        Y                  Out     0.411     5.345       -         
sfrdatao_12_am[3]                                           Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_ns[3]                   CFG3        A                  In      -         5.828       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_ns[3]                   CFG3        Y                  Out     0.076     5.904       -         
N_184                                                       Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_d[3]                       CFG4        B                  In      -         6.387       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_d[3]                       CFG4        Y                  Out     0.143     6.530       -         
sfrdatao_d[3]                                               Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_1[3]     CFG3        C                  In      -         7.013       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_1[3]     CFG3        Y                  Out     0.200     7.213       -         
PRDATA_0_1[3]                                               Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[3]       CFG4        B                  In      -         7.696       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[3]       CFG4        Y                  Out     0.125     7.821       -         
N_58                                                        Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]           CFG3        C                  In      -         8.304       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]           CFG3        Y                  Out     0.182     8.486       -         
Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]           Net         -                  -       0.971     -           1         
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_RDATA[3]     In      -         9.458       -         
===================================================================================================================================
Total path delay (propagation time + setup) of 10.384 is 5.508(53.0%) logic and 4.876(47.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            1.268
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.732

    - Propagation time:                      9.051
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.319

    Number of logic level(s):                6
    Starting point:                          Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[3]
    Ending point:                            Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2]
    The start point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                          Pin                Pin               Arrival     No. of    
Name                                                        Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_ADDR[3]      Out     3.035     3.035       -         
Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[3]                        Net         -                  -       1.005     -           99        
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am_1_1[2]               CFG4        D                  In      -         4.040       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am_1_1[2]               CFG4        Y                  Out     0.411     4.451       -         
sfrdatao_12_am_1_1[2]                                       Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am[2]                   CFG4        D                  In      -         4.934       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am[2]                   CFG4        Y                  Out     0.411     5.345       -         
sfrdatao_12_am_0[2]                                         Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_ns[2]                   CFG3        A                  In      -         5.828       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_ns[2]                   CFG3        Y                  Out     0.076     5.904       -         
N_183                                                       Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_0[2]     CFG4        B                  In      -         6.387       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_0[2]     CFG4        Y                  Out     0.133     6.520       -         
PRDATA_0_1_1[2]                                             Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[2]       CFG4        D                  In      -         7.004       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[2]       CFG4        Y                  Out     0.411     7.414       -         
N_57                                                        Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[2]           CFG3        C                  In      -         7.898       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[2]           CFG3        Y                  Out     0.182     8.080       -         
Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]           Net         -                  -       0.971     -           1         
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_RDATA[2]     In      -         9.051       -         
===================================================================================================================================
Total path delay (propagation time + setup) of 10.319 is 5.926(57.4%) logic and 4.393(42.6%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.926
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.074

    - Propagation time:                      9.393
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.319

    Number of logic level(s):                7
    Starting point:                          Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[4]
    Ending point:                            Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                          Pin                Pin               Arrival     No. of    
Name                                                        Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_ADDR[4]      Out     3.187     3.187       -         
Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[4]                        Net         -                  -       0.999     -           44        
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am_1_1[3]               CFG4        C                  In      -         4.186       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am_1_1[3]               CFG4        Y                  Out     0.200     4.386       -         
sfrdatao_12_am_1_1[3]                                       Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am[3]                   CFG4        D                  In      -         4.870       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_am[3]                   CFG4        Y                  Out     0.411     5.280       -         
sfrdatao_12_am[3]                                           Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_ns[3]                   CFG3        A                  In      -         5.763       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_12_ns[3]                   CFG3        Y                  Out     0.076     5.839       -         
N_184                                                       Net         -                  -       0.483     -           1         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_d[3]                       CFG4        B                  In      -         6.322       -         
CORESDLC_0.u_sdlc.u_sfr.sfrdatao_d[3]                       CFG4        Y                  Out     0.143     6.465       -         
sfrdatao_d[3]                                               Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_1[3]     CFG3        C                  In      -         6.948       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_1[3]     CFG3        Y                  Out     0.200     7.148       -         
PRDATA_0_1[3]                                               Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[3]       CFG4        B                  In      -         7.632       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[3]       CFG4        Y                  Out     0.125     7.756       -         
N_58                                                        Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]           CFG3        C                  In      -         8.239       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]           CFG3        Y                  Out     0.182     8.422       -         
Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]           Net         -                  -       0.971     -           1         
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_RDATA[3]     In      -         9.393       -         
===================================================================================================================================
Total path delay (propagation time + setup) of 10.319 is 5.449(52.8%) logic and 4.870(47.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      10.000
    - Setup time:                            1.268
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         8.732

    - Propagation time:                      9.008
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.276

    Number of logic level(s):                6
    Starting point:                          Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[3]
    Ending point:                            Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[2]
    The start point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                          Pin                Pin               Arrival     No. of    
Name                                                        Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_ADDR[3]      Out     3.035     3.035       -         
Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[3]                        Net         -                  -       1.005     -           99        
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am_1_1[2]               CFG4        D                  In      -         4.040       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am_1_1[2]               CFG4        Y                  Out     0.411     4.451       -         
sfrdatao_12_am_1_1[2]                                       Net         -                  -       0.483     -           1         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am[2]                   CFG4        D                  In      -         4.934       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am[2]                   CFG4        Y                  Out     0.411     5.345       -         
sfrdatao_12_am[2]                                           Net         -                  -       0.483     -           1         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_ns[2]                   CFG3        A                  In      -         5.828       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_ns[2]                   CFG3        Y                  Out     0.076     5.904       -         
N_186                                                       Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_0[2]     CFG4        A                  In      -         6.387       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_0[2]     CFG4        Y                  Out     0.090     6.477       -         
PRDATA_0_1_1[2]                                             Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[2]       CFG4        D                  In      -         6.960       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[2]       CFG4        Y                  Out     0.411     7.371       -         
N_57                                                        Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[2]           CFG3        C                  In      -         7.854       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[2]           CFG3        Y                  Out     0.182     8.036       -         
Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]           Net         -                  -       0.971     -           1         
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_RDATA[2]     In      -         9.008       -         
===================================================================================================================================
Total path delay (propagation time + setup) of 10.276 is 5.883(57.3%) logic and 4.393(42.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      10.000
    - Setup time:                            0.926
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.074

    - Propagation time:                      9.348
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.274

    Number of logic level(s):                7
    Starting point:                          Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[3]
    Ending point:                            Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
    The start point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
    The end   point is clocked by            Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

Instance / Net                                                          Pin                Pin               Arrival     No. of    
Name                                                        Type        Name               Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_ADDR[3]      Out     3.035     3.035       -         
Core_SDLC_sb_0_AMBA_SLAVE_1_PADDR[3]                        Net         -                  -       1.005     -           99        
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am_1_1[3]               CFG4        D                  In      -         4.040       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am_1_1[3]               CFG4        Y                  Out     0.411     4.451       -         
sfrdatao_12_am_1_1[3]                                       Net         -                  -       0.483     -           1         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am[3]                   CFG4        D                  In      -         4.934       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_am[3]                   CFG4        Y                  Out     0.411     5.345       -         
sfrdatao_12_am_0[3]                                         Net         -                  -       0.483     -           1         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_ns[3]                   CFG3        A                  In      -         5.828       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_12_ns[3]                   CFG3        Y                  Out     0.076     5.904       -         
N_187                                                       Net         -                  -       0.483     -           1         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_d_ns[3]                    CFG3        B                  In      -         6.387       -         
CORESDLC_1.u_sdlc.u_sfr.sfrdatao_d_ns[3]                    CFG3        Y                  Out     0.143     6.530       -         
sfrdatao_d_ns[3]                                            Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_1[3]     CFG3        A                  In      -         7.013       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO_1[3]     CFG3        Y                  Out     0.090     7.103       -         
PRDATA_0_1[3]                                               Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[3]       CFG4        B                  In      -         7.586       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_RNO[3]       CFG4        Y                  Out     0.125     7.711       -         
N_58                                                        Net         -                  -       0.483     -           1         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]           CFG3        C                  In      -         8.194       -         
Core_SDLC_sb_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA[3]           CFG3        Y                  Out     0.182     8.376       -         
Core_SDLC_sb_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]           Net         -                  -       0.971     -           1         
Core_SDLC_sb_0.Core_SDLC_sb_MSS_0.MSS_ADLIB_INST            MSS_075     F_HM0_RDATA[3]     In      -         9.348       -         
===================================================================================================================================
Total path delay (propagation time + setup) of 10.274 is 5.398(52.5%) logic and 4.876(47.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                        Starting                                                                Arrival          
Instance                                Reference     Type        Pin           Net                             Time        Slack
                                        Clock                                                                                    
---------------------------------------------------------------------------------------------------------------------------------
FCCC_0.CCC_INST                         System        CCC         GL0           GL0_net                         0.000       7.509
CORESDLC_1.u_rx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT_2[0]     0.000       8.526
CORESDLC_1.u_tx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT_1[0]     0.000       8.526
CORESDLC_1.u_rx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT_2[0]     0.000       8.526
CORESDLC_0.u_rx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT_0[0]     0.000       8.526
CORESDLC_0.u_tx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT[0]       0.000       8.526
CORESDLC_0.u_rx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT_0[0]     0.000       8.526
CORESDLC_0.u_tx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT[0]       0.000       8.526
CORESDLC_1.u_tx_ram.store_store_0_0     System        RAM1K18     A_DOUT[0]     store_store_0_0_A_DOUT_1[0]     0.000       8.526
CORESDLC_1.u_tx_ram.store_store_0_0     System        RAM1K18     A_DOUT[1]     store_store_0_0_A_DOUT_1[1]     0.000       8.526
=================================================================================================================================


Ending Points with Worst Slack
******************************

                                                  Starting                                       Required          
Instance                                          Reference     Type     Pin      Net            Time         Slack
                                                  Clock                                                            
-------------------------------------------------------------------------------------------------------------------
Core_SDLC_sb_0.CCC_0.CCC_INST                     System        CCC      CLK0     FCCC_0_GL0     10.000       7.509
CORESDLC_1.u_sdlc.u_receive.u_fifo.idatao[0]      System        SLE      D        rdib[0]        9.778        8.526
CORESDLC_0.u_sdlc.u_receive.u_fifo.idatao[0]      System        SLE      D        rdib[0]        9.778        8.526
CORESDLC_1.u_sdlc.u_transmit.u_fifo.idatao[0]     System        SLE      D        tdib[0]        9.778        8.526
CORESDLC_0.u_sdlc.u_transmit.u_fifo.idatao[0]     System        SLE      D        tdib[0]        9.778        8.526
CORESDLC_0.u_sdlc.u_receive.u_fifo.idatao[1]      System        SLE      D        rdib[1]        9.778        8.526
CORESDLC_1.u_sdlc.u_transmit.u_fifo.idatao[1]     System        SLE      D        tdib[1]        9.778        8.526
CORESDLC_1.u_sdlc.u_receive.u_fifo.idatao[1]      System        SLE      D        rdib[1]        9.778        8.526
CORESDLC_0.u_sdlc.u_transmit.u_fifo.idatao[1]     System        SLE      D        tdib[1]        9.778        8.526
CORESDLC_1.u_sdlc.u_receive.u_fifo.idatao[2]      System        SLE      D        rdib[2]        9.778        8.526
===================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      2.491
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 7.509

    Number of logic level(s):                1
    Starting point:                          FCCC_0.CCC_INST / GL0
    Ending point:                            Core_SDLC_sb_0.CCC_0.CCC_INST / CLK0
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                              Type       Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
FCCC_0.CCC_INST                   CCC        GL0      Out     0.000     0.000       -         
GL0_net                           Net        -        -       0.971     -           1         
FCCC_0.GL0_INST                   CLKINT     A        In      -         0.971       -         
FCCC_0.GL0_INST                   CLKINT     Y        Out     0.548     1.520       -         
FCCC_0_GL0                        Net        -        -       0.971     -           1         
Core_SDLC_sb_0.CCC_0.CCC_INST     CCC        CLK0     In      -         2.491       -         
==============================================================================================
Total path delay (propagation time + setup) of 2.491 is 0.548(22.0%) logic and 1.943(78.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for Core_SDLC 

Mapping to part: m2s090tsfbga676-1
Cell usage:
CCC             2 uses
CLKINT          3 uses
MSS_075         1 use
SYSRESET        1 use
CFG1           4 uses
CFG2           247 uses
CFG3           293 uses
CFG4           513 uses

Carry primitives used for arithmetic functions:
ARI1           34 uses


Sequential Cells: 
SLE            657 uses

DSP Blocks:    0

I/O ports: 15
I/O primitives: 14
INBUF          7 uses
OUTBUF         5 uses
TRIBUFF        2 uses


Global Clock Buffers: 3


RAM/ROM usage summary
Block Rams (RAM1K18) : 4

Total LUTs:    1091

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:05s; Memory used current: 53MB peak: 195MB)

Process took 0h:00m:11s realtime, 0h:00m:05s cputime
# Wed Apr 08 12:05:34 2015

###########################################################]