Project Settings |
---|
Project Name | Core_SDLC_syn | Implementation Name | synthesis |
Top Module | Core_SDLC | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 10000 |
Disable I/O Insertion | 0 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
Compile Input | Complete |
46 |
118 |
0 |
- |
0m:03s |
- |
4/8/2015 12:05:15 PM |
Pre-mapping | Complete |
88 |
2 |
0 |
0m:00s |
0m:04s |
137MB |
4/8/2015 12:05:22 PM |
Map & Optimize | Complete |
32 |
14 |
0 |
0m:05s |
0m:11s |
195MB |
4/8/2015 12:05:34 PM |
Area Summary |
|
Carry Cells | 34 |
Sequential Cells | 657 |
DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 14 |
Global Clock Buffers | 3 |
Block Rams (RAM1K18)
(v_ram) | 4 |
LUTs
(total_luts) | 1091 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
Core_SDLC_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 96.3 MHz | -0.384 |
System | 100.0 MHz | 401.4 MHz | 7.509 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|