Project Settings
Project Name m2s060_som_syn Implementation Name synthesis
Top Module m2s060_som Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 40 59 0 - 0m:00s - 08.11.2015
18:12:19
(premap)Complete 35 7 0 0m:00s 0m:00s 137MB 08.11.2015
18:12:21
(fpga_mapper)Complete 32 51 0 0m:01s 0m:01s 136MB 08.11.2015
18:12:23
Multi-srs Generator Complete0m:01s08.11.2015
18:12:21

Area Summary
Carry Cells 14 Sequential Cells 106
DSP Blocks (MACC) (dsp_used) 0 I/O Cells 97
Global Clock Buffers 6 LUTs (total_luts) 70

Timing Summary
Clock NameReq FreqEst FreqSlack
m2s060_som_sb_CCC_0_FCCC|GL0_net_inferred_clock100.0 MHz407.0 MHz7.543
m2s060_som_sb_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock100.0 MHz355.3 MHz7.186
m2s060_som_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock100.0 MHz130.0 MHz1.286
m2s060_som|MAC_MII_RX_CLK100.0 MHzNANA
m2s060_som|MAC_MII_TX_CLK100.0 MHzNANA
System100.0 MHz895.2 MHz8.883

Optimizations Summary
Combined Clock Conversion 4 / 1