KEY LIBERO "11.4"
KEY CAPTURE "11.4.0.112"
KEY DEFAULT_IMPORT_LOC "C:\Actelprj\A3P_Verilog_labs\lab2"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0"
KEY HDLTechnology "VERILOG"
KEY VendorTechnology_Family "SmartFusion2"
KEY VendorTechnology_Die "PA4M2500"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "-1"
KEY VendorTechnology_DieVoltage "1.2"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
KEY VendorTechnology_IO_DEFT_STD "LVCMOS25"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_25"
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_VCCI_1.2_VOLTR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "D:\11.4_UPDATES\EvaluationKit\svn\PCIE_Demo"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "PCIe_Demo_top::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
COREAHBLITE_LIB
ENDLIST
LIST LIBRARY_COREAHBLITE_LIB
ALIAS=..\component\Actel\DirectCore\CoreAHBLite\5.2.1\mti\user_vlog\COREAHBLITE_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
CUSTOMPATH=false
ENDLIST
LIST FileManager
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ENDFILE
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MODULE_UNDER_TEST="testbench"
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BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
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END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
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BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
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END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
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PARENT="<project>\component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
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BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
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USE_FOR_ANY_TOOL="FALSE"
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BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
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BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
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PARENT="<project>\component\work\PCIe_Demo_top\PCIe_Demo_top.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1406265503"
SIZE="1050"
PARENT="<project>\component\work\PCIe_Demo_top\PCIe_Demo_top.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1405672561"
SIZE="734"
PARENT="<project>\component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\testbench_presynth_simulation.log,log"
STATE="utd"
TIME="1406265630"
SIZE="87984"
ENDFILE
VALUE "<project>\simulation\user.bfm,sim"
STATE="utd"
TIME="1385135556"
SIZE="555"
PARENT="<project>\component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\wave.do,do"
STATE="utd"
TIME="1385287879"
SIZE="1274"
ENDFILE
VALUE "<project>\stimulus\testbench.v,tb_hdl"
STATE="utd"
TIME="1406264518"
SIZE="2297"
ENDFILE
VALUE "<project>\synthesis\PCIe_Demo_top.edn,syn_edn"
STATE="utd"
TIME="1405672751"
SIZE="1017055"
ENDFILE
VALUE "<project>\synthesis\PCIe_Demo_top.so,so"
STATE="utd"
TIME="1405672751"
SIZE="239"
ENDFILE
VALUE "<project>\synthesis\PCIe_Demo_top.v,syn_hdl"
STATE="utd"
TIME="1405672766"
SIZE="401084"
ENDFILE
VALUE "<project>\synthesis\PCIe_Demo_top_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1405672751"
SIZE="1688"
ENDFILE
VALUE "<project>\synthesis\PCIe_Demo_top_syn.prj,prj"
STATE="utd"
TIME="1405672753"
SIZE="4195"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "PCIe_Demo::work"
FILE "<project>\component\work\PCIe_Demo\PCIe_Demo.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "PCIe_Demo_MSS::work"
FILE "<project>\component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST "PCIe_Demo_top::work"
FILE "<project>\component\work\PCIe_Demo_top\PCIe_Demo_top.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\PCIe_Demo_top\SERDES_IF_0\SERDESIF_1_init.bfm,sim"
VALUE "<project>\component\work\PCIe_Demo_top\SERDES_IF_0\SERDESIF_1_user.bfm,sim"
VALUE "<project>\component\work\PCIe_Demo_top\SERDES_IF_0\SERDESIF_1_compile_bfm.tcl,sim"
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\simulation\SERDESIF_0_init.bfm,sim"
VALUE "<project>\simulation\SERDESIF_0_user.bfm,sim"
VALUE "<project>\simulation\SERDESIF_0_compile_bfm.tcl,sim"
VALUE "<project>\simulation\SERDESIF_1_init.bfm,sim"
VALUE "<project>\simulation\SERDESIF_1_user.bfm,sim"
VALUE "<project>\simulation\SERDESIF_1_compile_bfm.tcl,sim"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\stimulus\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\PCIe_Demo_top.edn,syn_edn)=StateSuccess
ideSYNTHESIS(<project>\synthesis\PCIe_Demo_top.vm,syn_vm)=StateFailure
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST PinReports
VALUE "<project>\designer\PCIe_Demo_top\PCIe_Demo_top_pinrpt_name.rpt,log"
VALUE "<project>\designer\PCIe_Demo_top\PCIe_Demo_top_pinrpt_number.rpt,log"
VALUE "<project>\designer\PCIe_Demo_top\PCIe_Demo_top_bankrpt.rpt,log"
VALUE "<project>\designer\PCIe_Demo_top\PCIe_Demo_top_ioff.xml,log"
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST PCIe_Demo_top
VALUE "<project>\stimulus\testbench.v,tb_hdl"
ENDLIST
LIST PCIe_Demo
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST PCIe_Demo_top
VALUE "<project>\component\work\PCIe_Demo_top\SERDES_IF_0\SERDESIF_1_init.bfm,sim"
VALUE "<project>\component\work\PCIe_Demo_top\SERDES_IF_0\SERDESIF_1_user.bfm,sim"
VALUE "<project>\component\work\PCIe_Demo_top\SERDES_IF_0\SERDESIF_1_compile_bfm.tcl,sim"
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\simulation\SERDESIF_0_init.bfm,sim"
VALUE "<project>\simulation\SERDESIF_0_user.bfm,sim"
VALUE "<project>\simulation\SERDESIF_0_compile_bfm.tcl,sim"
VALUE "<project>\simulation\SERDESIF_1_init.bfm,sim"
VALUE "<project>\simulation\SERDESIF_1_user.bfm,sim"
VALUE "<project>\simulation\SERDESIF_1_compile_bfm.tcl,sim"
ENDLIST
LIST PCIe_Demo
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreahblite_usertb_include.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>\simulation\coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAHBLite\5.2.1\mti\scripts\wave_user.do,do"
ENDLIST
LIST PCIe_Demo_MSS
VALUE "<project>\simulation\CM3_compile_bfm.tcl,sim"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\simulation\peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=true
Type=max
RunTime=220us
Resolution=1fs
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=true
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="11.4_Synplify"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="\\idm\tools\releases\production\Synopsys\Synplify\pc\synplify_I201309MSP1-1\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="11.4_Modelsim"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="\\idm\tools\releases\production\Mentor\ModelSim\pc\modelsim_ME_10.3a\modeltech\win32acoem\modelsim.exe"
PARAM=" -l testbench_presynth_simulation.log "
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="D:\Microsemi\Libero_v11.4\Designer\bin\FlashPro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="D:\Microsemi\Libero_v11.4\Synopsys\Identify_me_I201309MSP1-2\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "PCIe_Demo::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "PCIe_Demo_top::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>\synthesis\PCIe_Demo_top.edn,syn_edn)=StateSuccess
ideSYNTHESIS(<project>\synthesis\PCIe_Demo_top.vm,syn_vm)=StateFailure
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Run PROGRAM Action:PCIe_Demo_top_PROGRAM.log
SmartDesign;PCIe_Demo_top;0
StartPage;StartPage;0
ACTIVEVIEW;PCIe_Demo_top
ENDLIST
LIST ModuleSubBlockList
LIST "CoreConfigP::work","component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v","FALSE","FALSE"
ENDLIST
LIST "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v","FALSE","FALSE"
SUBBLOCK "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v","FALSE","FALSE"
ENDLIST
LIST "coreresetp_pcie_hotreset::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v","FALSE","FALSE"
ENDLIST
LIST "DEBOUNCE::work","hdl\Debounce.v","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "SmartFusion2_CMSIS::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_GPIO_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_025::work","component\work\PCIe_Demo_MSS\PCIe_Demo_MSS_syn.v","FALSE","FALSE"
ENDLIST
LIST "PCIe_Demo::work","component\work\PCIe_Demo\PCIe_Demo.v","TRUE","FALSE"
SUBBLOCK "PCIe_Demo_CCC_0_FCCC::work","component\work\PCIe_Demo\CCC_0\PCIe_Demo_CCC_0_FCCC.v","FALSE","FALSE"
SUBBLOCK "CoreConfigP::work","component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v","FALSE","FALSE"
SUBBLOCK "CoreResetP::work","component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v","FALSE","FALSE"
SUBBLOCK "PCIe_Demo_FABOSC_0_OSC::work","component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "PCIe_Demo_MSS::work","component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.v","TRUE","FALSE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
ENDLIST
LIST "PCIe_Demo_CCC_0_FCCC::work","component\work\PCIe_Demo\CCC_0\PCIe_Demo_CCC_0_FCCC.v","FALSE","FALSE"
ENDLIST
LIST "PCIe_Demo_FABOSC_0_OSC::work","component\work\PCIe_Demo\FABOSC_0\PCIe_Demo_FABOSC_0_OSC.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "PCIe_Demo_MSS::work","component\work\PCIe_Demo_MSS\PCIe_Demo_MSS.v","TRUE","FALSE"
SUBBLOCK "MSS_025::work","component\work\PCIe_Demo_MSS\PCIe_Demo_MSS_syn.v","FALSE","FALSE"
ENDLIST
LIST "PCIe_Demo_top::work","component\work\PCIe_Demo_top\PCIe_Demo_top.v","TRUE","FALSE"
SUBBLOCK "DEBOUNCE::work","hdl\Debounce.v","FALSE","FALSE"
SUBBLOCK "PCIe_Demo::work","component\work\PCIe_Demo\PCIe_Demo.v","TRUE","FALSE"
SUBBLOCK "PCIe_Demo_top_SERDES_IF_0_SERDES_IF::work","component\work\PCIe_Demo_top\SERDES_IF_0\PCIe_Demo_top_SERDES_IF_0_SERDES_IF.v","FALSE","FALSE"
ENDLIST
LIST "PCIe_Demo_top_SERDES_IF_0_SERDES_IF::work","component\work\PCIe_Demo_top\SERDES_IF_0\PCIe_Demo_top_SERDES_IF_0_SERDES_IF.v","FALSE","FALSE"
SUBBLOCK "SERDESIF_0::work","component\work\PCIe_Demo_top\SERDES_IF_0\PCIe_Demo_top_SERDES_IF_0_SERDES_IF_syn.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "SERDESIF_0::work","component\work\PCIe_Demo_top\SERDES_IF_0\PCIe_Demo_top_SERDES_IF_0_SERDES_IF_syn.v","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_CMSIS::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_GPIO_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_HPDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_System_Services_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "SmartFusion2_MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\1.0.102\osc_comps.v","FALSE","FALSE"
ENDLIST
LIST "testbench::work","stimulus\testbench.v","FALSE","TRUE"
SUBBLOCK "PCIe_Demo_top::work","component\work\PCIe_Demo_top\PCIe_Demo_top.v","TRUE","FALSE"
ENDLIST
LIST "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_matrix4x16.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_addrdec.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_defaultslavesm.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_masterstage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_ADDRDEC::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_addrdec.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_DEFAULTSLAVESM::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_defaultslavesm.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_matrix4x16.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_masterstage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_slavestage.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_slavearbiter.v","FALSE","FALSE"
ENDLIST
LIST "COREAHBLITE_SLAVESTAGE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_slavestage.v","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_SLAVEARBITER::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite_slavearbiter.v","FALSE","FALSE"
ENDLIST
LIST "BFM_AHBL::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
SUBBLOCK "BFM_MAIN::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFM_AHBSLAVE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBSLAVEEXT::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_AHBSLAVEEXT::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_MAIN::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\core\coreahblite.v","FALSE","FALSE"
SUBBLOCK "BFM_AHBL::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
SUBBLOCK "BFM_AHBSLAVE::COREAHBLITE_LIB","component\Actel\DirectCore\CoreAHBLite\5.2.1\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
LIST "PCIe_Demo_top::work"
ACTIVETESTBENCH "testbench::work","stimulus\testbench.v","FALSE"
ENDLIST
ENDLIST
