# ===========================================================
# Created by Microsemi SmartDesign Fri Jul 18 14:07:07 2014
# 
# Warning: Do not modify this file, it may lead to unexpected 
#          simulation failures in your design.
#
# ===========================================================

#------------------------------------------------------------
# SERDESIF_0  Initialization procedure
#------------------------------------------------------------


procedure SERDESIF_0_init;
write w SERDESIF_0 0x2030 0x11AA11AA; // SYSTEM_CONFIG_PCIE_0
write w SERDESIF_0 0x2034 0x000011AA; // SYSTEM_CONFIG_PCIE_1
write w SERDESIF_0 0x20a8 0xA5; // SYSTEM_DEBUG_MODE_KEY
write w SERDESIF_0 0x2028 0x11E; // SYSTEM_CONFIG_PHY_MODE_1
write w SERDESIF_0 0x1008 0xF8; // LANE0_RXIDLE_MAX_ERRCNT_THR
write w SERDESIF_0 0x1050 0x20; // LANE0_TX_PST_RATIO_DEEMP0_FULL
write w SERDESIF_0 0x1058 0x15; // LANE0_TX_PST_RATIO_DEEMP1_FULL
write w SERDESIF_0 0x1090 0x20; // LANE0_TX_PST_RATIO_DEEMP0_HALF
write w SERDESIF_0 0x1098 0x15; // LANE0_TX_PST_RATIO_DEEMP1_HALF
write w SERDESIF_0 0x1200 0x1; // LANE0_UPDATE_SETTINGS
write w SERDESIF_0 0x2028 0xF1E; // SYSTEM_CONFIG_PHY_MODE_1
return

#ifndef USE_SERDESIF
#define USE_SERDESIF
#endif

#define USE_SERDESIF_0_PCIE_0

#define SERDESIF_0_lane_x_pma_status LANE_0_PMA_STATUS
#define SERDESIF_0_lane_x_cfg_phy_mode_1 0x100

procedure SERDESIF_0_init_pcie;
write w SERDESIF_0 0x002c 0x110A1556; // PCIE_SUBSYSTEM_ID
write w SERDESIF_0 0x0048 0x48018001; // PCIE_POWER_MGT_CAPABILITY
write w SERDESIF_0 0x0100 0x40000000; // PCIE_AXI_MASTER_WINDOW0_0
write w SERDESIF_0 0x0104 0xFFF00001; // PCIE_AXI_MASTER_WINDOW0_1
write w SERDESIF_0 0x0108 0x1; // PCIE_AXI_MASTER_WINDOW0_2
write w SERDESIF_0 0x0110 0x20000000; // PCIE_AXI_MASTER_WINDOW1_0
write w SERDESIF_0 0x0114 0xFFFF0001; // PCIE_AXI_MASTER_WINDOW1_1
write w SERDESIF_0 0x0118 0x2; // PCIE_AXI_MASTER_WINDOW1_2
return

