//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Fri Jul 18 14:07:08 2014
// Version: v11.4 11.4.0.112
//////////////////////////////////////////////////////////////////////

`timescale 1 ns/100 ps

// PCIe_Demo_top
module PCIe_Demo_top(
    // Inputs
    CLK0,
    DEVRST_N,
    GPIO_10_F2M,
    GPIO_11_F2M,
    GPIO_8_F2M,
    GPIO_9_F2M,
    REFCLK0_N,
    REFCLK0_P,
    RXD0_N,
    RXD0_P,
    RXD1_N,
    RXD1_P,
    RXD2_N,
    RXD2_P,
    RXD3_N,
    RXD3_P,
    SDIF0_PERST_N,
    SWITCH,
    // Outputs
    GPIO_0_M2F,
    GPIO_1_M2F,
    GPIO_2_M2F,
    GPIO_3_M2F,
    GPIO_4_M2F,
    GPIO_5_M2F,
    GPIO_6_M2F,
    GPIO_7_M2F,
    TXD0_N,
    TXD0_P,
    TXD1_N,
    TXD1_P,
    TXD2_N,
    TXD2_P,
    TXD3_N,
    TXD3_P
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  CLK0;
input  DEVRST_N;
input  GPIO_10_F2M;
input  GPIO_11_F2M;
input  GPIO_8_F2M;
input  GPIO_9_F2M;
input  REFCLK0_N;
input  REFCLK0_P;
input  RXD0_N;
input  RXD0_P;
input  RXD1_N;
input  RXD1_P;
input  RXD2_N;
input  RXD2_P;
input  RXD3_N;
input  RXD3_P;
input  SDIF0_PERST_N;
input  SWITCH;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output GPIO_0_M2F;
output GPIO_1_M2F;
output GPIO_2_M2F;
output GPIO_3_M2F;
output GPIO_4_M2F;
output GPIO_5_M2F;
output GPIO_6_M2F;
output GPIO_7_M2F;
output TXD0_N;
output TXD0_P;
output TXD1_N;
output TXD1_P;
output TXD2_N;
output TXD2_P;
output TXD3_N;
output TXD3_P;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          CLK0;
wire          DEBOUNCE_0_INTERRUPT;
wire          DEVRST_N;
wire          GPIO_0_M2F_0;
wire          GPIO_1_M2F_0;
wire          GPIO_2_M2F_0;
wire          GPIO_3_M2F_0;
wire          GPIO_4_M2F_0;
wire          GPIO_5_M2F_0;
wire          GPIO_6_M2F_0;
wire          GPIO_7_M2F_0;
wire          GPIO_8_F2M;
wire          GPIO_9_F2M;
wire          GPIO_10_F2M;
wire          GPIO_11_F2M;
wire          PCIe_Demo_0_FIC_0_CLK;
wire          PCIe_Demo_0_INIT_APB_S_PCLK;
wire          PCIe_Demo_0_INIT_APB_S_PRESET_N;
wire          PCIe_Demo_0_MSS_READY;
wire          PCIe_Demo_0_SDIF0_CORE_RESET_N;
wire          PCIe_Demo_0_SDIF0_INIT_APB_PENABLE;
wire   [31:0] PCIe_Demo_0_SDIF0_INIT_APB_PRDATA;
wire          PCIe_Demo_0_SDIF0_INIT_APB_PREADY;
wire          PCIe_Demo_0_SDIF0_INIT_APB_PSELx;
wire          PCIe_Demo_0_SDIF0_INIT_APB_PSLVERR;
wire   [31:0] PCIe_Demo_0_SDIF0_INIT_APB_PWDATA;
wire          PCIe_Demo_0_SDIF0_INIT_APB_PWRITE;
wire          PCIe_Demo_0_SDIF0_PHY_RESET_N;
wire          REFCLK0_N;
wire          REFCLK0_P;
wire          RXD0_N;
wire          RXD0_P;
wire          RXD1_N;
wire          RXD1_P;
wire          RXD2_N;
wire          RXD2_P;
wire          RXD3_N;
wire          RXD3_P;
wire          SDIF0_PERST_N;
wire   [31:0] SERDES_IF_0_AHB_MASTER_HADDR;
wire   [31:0] SERDES_IF_0_AHB_MASTER_HRDATA;
wire          SERDES_IF_0_AHB_MASTER_HREADY;
wire   [1:0]  SERDES_IF_0_AHB_MASTER_HTRANS;
wire   [31:0] SERDES_IF_0_AHB_MASTER_HWDATA;
wire          SERDES_IF_0_AHB_MASTER_HWRITE;
wire          SERDES_IF_0_SPLL_LOCK;
wire          SWITCH;
wire          TXD0_N_net_0;
wire          TXD0_P_net_0;
wire          TXD1_N_net_0;
wire          TXD1_P_net_0;
wire          TXD2_N_net_0;
wire          TXD2_P_net_0;
wire          TXD3_N_net_0;
wire          TXD3_P_net_0;
wire          TXD0_P_net_1;
wire          TXD0_N_net_1;
wire          TXD1_P_net_1;
wire          TXD1_N_net_1;
wire          TXD2_P_net_1;
wire          TXD2_N_net_1;
wire          TXD3_P_net_1;
wire          TXD3_N_net_1;
wire          GPIO_0_M2F_0_net_0;
wire          GPIO_1_M2F_0_net_0;
wire          GPIO_2_M2F_0_net_0;
wire          GPIO_3_M2F_0_net_0;
wire          GPIO_4_M2F_0_net_0;
wire          GPIO_5_M2F_0_net_0;
wire          GPIO_6_M2F_0_net_0;
wire          GPIO_7_M2F_0_net_0;
wire   [3:0]  PCIE_INTERRUPT_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
wire   [3:1]  PCIE_INTERRUPT_const_net_0;
wire   [19:0] EPCS_0_TX_DATA_const_net_0;
wire   [19:0] EPCS_1_TX_DATA_const_net_0;
wire   [19:0] EPCS_2_TX_DATA_const_net_0;
wire   [19:0] EPCS_3_TX_DATA_const_net_0;
wire   [9:0]  SGMII_TX_DATA_const_net_0;
wire          GND_net;
wire   [3:0]  AXI_M_BID_const_net_0;
wire   [1:0]  AXI_M_BRESP_const_net_0;
wire   [3:0]  AXI_M_RID_const_net_0;
wire   [63:0] AXI_M_RDATA_const_net_0;
wire   [1:0]  AXI_M_RRESP_const_net_0;
wire   [3:0]  AXI_S_AWID_const_net_0;
wire   [31:0] AXI_S_AWADDR_const_net_0;
wire   [3:0]  AXI_S_AWLEN_const_net_0;
wire   [1:0]  AXI_S_AWSIZE_const_net_0;
wire   [1:0]  AXI_S_AWBURST_const_net_0;
wire   [1:0]  AXI_S_AWLOCK_const_net_0;
wire   [3:0]  AXI_S_WID_const_net_0;
wire   [7:0]  AXI_S_WSTRB_const_net_0;
wire   [63:0] AXI_S_WDATA_const_net_0;
wire   [3:0]  AXI_S_ARID_const_net_0;
wire   [31:0] AXI_S_ARADDR_const_net_0;
wire   [3:0]  AXI_S_ARLEN_const_net_0;
wire   [1:0]  AXI_S_ARSIZE_const_net_0;
wire   [1:0]  AXI_S_ARBURST_const_net_0;
wire   [1:0]  AXI_S_ARLOCK_const_net_0;
wire   [31:0] AHB_S_HADDR_const_net_0;
wire   [1:0]  AHB_S_HBURST_const_net_0;
wire   [1:0]  AHB_S_HSIZE_const_net_0;
wire   [1:0]  AHB_S_HTRANS_const_net_0;
wire   [31:0] AHB_S_HWDATA_const_net_0;
wire   [4:0]  XAUI_MMD_PRTAD_const_net_0;
wire   [4:0]  XAUI_MMD_DEVID_const_net_0;
wire   [63:0] XAUI_TXD_const_net_0;
wire   [7:0]  XAUI_TXC_const_net_0;
wire   [3:0]  AMBA_MASTER_0_HPROT_M0_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [13:2] PCIe_Demo_0_SDIF0_INIT_APB_PADDR_0_13to2;
wire   [13:2] PCIe_Demo_0_SDIF0_INIT_APB_PADDR_0;
wire   [15:2] PCIe_Demo_0_SDIF0_INIT_APB_PADDR;
wire   [1:0]  SERDES_IF_0_AHB_MASTER_HBURST;
wire   [2:2]  SERDES_IF_0_AHB_MASTER_HBURST_0_2to2;
wire   [1:0]  SERDES_IF_0_AHB_MASTER_HBURST_0_1to0;
wire   [2:0]  SERDES_IF_0_AHB_MASTER_HBURST_0;
wire   [0:0]  SERDES_IF_0_AHB_MASTER_HRESP_0_0to0;
wire          SERDES_IF_0_AHB_MASTER_HRESP_0;
wire   [1:0]  SERDES_IF_0_AHB_MASTER_HRESP;
wire   [1:0]  SERDES_IF_0_AHB_MASTER_HSIZE;
wire   [2:2]  SERDES_IF_0_AHB_MASTER_HSIZE_0_2to2;
wire   [1:0]  SERDES_IF_0_AHB_MASTER_HSIZE_0_1to0;
wire   [2:0]  SERDES_IF_0_AHB_MASTER_HSIZE_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net                            = 1'b1;
assign PCIE_INTERRUPT_const_net_0         = 3'h0;
assign EPCS_0_TX_DATA_const_net_0         = 20'h00000;
assign EPCS_1_TX_DATA_const_net_0         = 20'h00000;
assign EPCS_2_TX_DATA_const_net_0         = 20'h00000;
assign EPCS_3_TX_DATA_const_net_0         = 20'h00000;
assign SGMII_TX_DATA_const_net_0          = 10'h000;
assign GND_net                            = 1'b0;
assign AXI_M_BID_const_net_0              = 4'h0;
assign AXI_M_BRESP_const_net_0            = 2'h0;
assign AXI_M_RID_const_net_0              = 4'h0;
assign AXI_M_RDATA_const_net_0            = 64'h0000000000000000;
assign AXI_M_RRESP_const_net_0            = 2'h0;
assign AXI_S_AWID_const_net_0             = 4'h0;
assign AXI_S_AWADDR_const_net_0           = 32'h00000000;
assign AXI_S_AWLEN_const_net_0            = 4'h0;
assign AXI_S_AWSIZE_const_net_0           = 2'h0;
assign AXI_S_AWBURST_const_net_0          = 2'h0;
assign AXI_S_AWLOCK_const_net_0           = 2'h0;
assign AXI_S_WID_const_net_0              = 4'h0;
assign AXI_S_WSTRB_const_net_0            = 8'h00;
assign AXI_S_WDATA_const_net_0            = 64'h0000000000000000;
assign AXI_S_ARID_const_net_0             = 4'h0;
assign AXI_S_ARADDR_const_net_0           = 32'h00000000;
assign AXI_S_ARLEN_const_net_0            = 4'h0;
assign AXI_S_ARSIZE_const_net_0           = 2'h0;
assign AXI_S_ARBURST_const_net_0          = 2'h0;
assign AXI_S_ARLOCK_const_net_0           = 2'h0;
assign AHB_S_HADDR_const_net_0            = 32'h00000000;
assign AHB_S_HBURST_const_net_0           = 2'h0;
assign AHB_S_HSIZE_const_net_0            = 2'h0;
assign AHB_S_HTRANS_const_net_0           = 2'h0;
assign AHB_S_HWDATA_const_net_0           = 32'h00000000;
assign XAUI_MMD_PRTAD_const_net_0         = 5'h00;
assign XAUI_MMD_DEVID_const_net_0         = 5'h00;
assign XAUI_TXD_const_net_0               = 64'h0000000000000000;
assign XAUI_TXC_const_net_0               = 8'h00;
assign AMBA_MASTER_0_HPROT_M0_const_net_0 = 4'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TXD0_P_net_1       = TXD0_P_net_0;
assign TXD0_P             = TXD0_P_net_1;
assign TXD0_N_net_1       = TXD0_N_net_0;
assign TXD0_N             = TXD0_N_net_1;
assign TXD1_P_net_1       = TXD1_P_net_0;
assign TXD1_P             = TXD1_P_net_1;
assign TXD1_N_net_1       = TXD1_N_net_0;
assign TXD1_N             = TXD1_N_net_1;
assign TXD2_P_net_1       = TXD2_P_net_0;
assign TXD2_P             = TXD2_P_net_1;
assign TXD2_N_net_1       = TXD2_N_net_0;
assign TXD2_N             = TXD2_N_net_1;
assign TXD3_P_net_1       = TXD3_P_net_0;
assign TXD3_P             = TXD3_P_net_1;
assign TXD3_N_net_1       = TXD3_N_net_0;
assign TXD3_N             = TXD3_N_net_1;
assign GPIO_0_M2F_0_net_0 = GPIO_0_M2F_0;
assign GPIO_0_M2F         = GPIO_0_M2F_0_net_0;
assign GPIO_1_M2F_0_net_0 = GPIO_1_M2F_0;
assign GPIO_1_M2F         = GPIO_1_M2F_0_net_0;
assign GPIO_2_M2F_0_net_0 = GPIO_2_M2F_0;
assign GPIO_2_M2F         = GPIO_2_M2F_0_net_0;
assign GPIO_3_M2F_0_net_0 = GPIO_3_M2F_0;
assign GPIO_3_M2F         = GPIO_3_M2F_0_net_0;
assign GPIO_4_M2F_0_net_0 = GPIO_4_M2F_0;
assign GPIO_4_M2F         = GPIO_4_M2F_0_net_0;
assign GPIO_5_M2F_0_net_0 = GPIO_5_M2F_0;
assign GPIO_5_M2F         = GPIO_5_M2F_0_net_0;
assign GPIO_6_M2F_0_net_0 = GPIO_6_M2F_0;
assign GPIO_6_M2F         = GPIO_6_M2F_0_net_0;
assign GPIO_7_M2F_0_net_0 = GPIO_7_M2F_0;
assign GPIO_7_M2F         = GPIO_7_M2F_0_net_0;
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign PCIE_INTERRUPT_net_0 = { 3'h0 , DEBOUNCE_0_INTERRUPT };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign PCIe_Demo_0_SDIF0_INIT_APB_PADDR_0_13to2 = PCIe_Demo_0_SDIF0_INIT_APB_PADDR[13:2];
assign PCIe_Demo_0_SDIF0_INIT_APB_PADDR_0 = { PCIe_Demo_0_SDIF0_INIT_APB_PADDR_0_13to2 };

assign SERDES_IF_0_AHB_MASTER_HBURST_0_2to2 = 1'b0;
assign SERDES_IF_0_AHB_MASTER_HBURST_0_1to0 = SERDES_IF_0_AHB_MASTER_HBURST[1:0];
assign SERDES_IF_0_AHB_MASTER_HBURST_0 = { SERDES_IF_0_AHB_MASTER_HBURST_0_2to2, SERDES_IF_0_AHB_MASTER_HBURST_0_1to0 };

assign SERDES_IF_0_AHB_MASTER_HRESP_0_0to0 = SERDES_IF_0_AHB_MASTER_HRESP[0:0];
assign SERDES_IF_0_AHB_MASTER_HRESP_0 = { SERDES_IF_0_AHB_MASTER_HRESP_0_0to0 };

assign SERDES_IF_0_AHB_MASTER_HSIZE_0_2to2 = 1'b0;
assign SERDES_IF_0_AHB_MASTER_HSIZE_0_1to0 = SERDES_IF_0_AHB_MASTER_HSIZE[1:0];
assign SERDES_IF_0_AHB_MASTER_HSIZE_0 = { SERDES_IF_0_AHB_MASTER_HSIZE_0_2to2, SERDES_IF_0_AHB_MASTER_HSIZE_0_1to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------DEBOUNCE
DEBOUNCE DEBOUNCE_0(
        // Inputs
        .CLK       ( PCIe_Demo_0_FIC_0_CLK ),
        .RESET_N   ( PCIe_Demo_0_MSS_READY ),
        .SWITCH    ( SWITCH ),
        // Outputs
        .INTERRUPT ( DEBOUNCE_0_INTERRUPT ) 
        );

//--------PCIe_Demo
PCIe_Demo PCIe_Demo_0(
        // Inputs
        .FAB_RESET_N                ( VCC_net ),
        .AMBA_MASTER_0_HADDR_M0     ( SERDES_IF_0_AHB_MASTER_HADDR ),
        .AMBA_MASTER_0_HTRANS_M0    ( SERDES_IF_0_AHB_MASTER_HTRANS ),
        .AMBA_MASTER_0_HWRITE_M0    ( SERDES_IF_0_AHB_MASTER_HWRITE ),
        .AMBA_MASTER_0_HSIZE_M0     ( SERDES_IF_0_AHB_MASTER_HSIZE_0 ),
        .AMBA_MASTER_0_HBURST_M0    ( SERDES_IF_0_AHB_MASTER_HBURST_0 ),
        .AMBA_MASTER_0_HPROT_M0     ( AMBA_MASTER_0_HPROT_M0_const_net_0 ), // tied to 4'h0 from definition
        .AMBA_MASTER_0_HWDATA_M0    ( SERDES_IF_0_AHB_MASTER_HWDATA ),
        .AMBA_MASTER_0_HMASTLOCK_M0 ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PRDATA               ( PCIe_Demo_0_SDIF0_INIT_APB_PRDATA ),
        .SDIF0_PREADY               ( PCIe_Demo_0_SDIF0_INIT_APB_PREADY ),
        .SDIF0_PSLVERR              ( PCIe_Demo_0_SDIF0_INIT_APB_PSLVERR ),
        .DEVRST_N                   ( DEVRST_N ),
        .SDIF0_SPLL_LOCK            ( SERDES_IF_0_SPLL_LOCK ),
        .SDIF0_PERST_N              ( SDIF0_PERST_N ),
        .CLK0                       ( CLK0 ),
        .GPIO_8_F2M                 ( GPIO_8_F2M ),
        .GPIO_9_F2M                 ( GPIO_9_F2M ),
        .GPIO_10_F2M                ( GPIO_10_F2M ),
        .GPIO_11_F2M                ( GPIO_11_F2M ),
        // Outputs
        .POWER_ON_RESET_N           (  ),
        .INIT_DONE                  (  ),
        .AMBA_MASTER_0_HRDATA_M0    ( SERDES_IF_0_AHB_MASTER_HRDATA ),
        .AMBA_MASTER_0_HREADY_M0    ( SERDES_IF_0_AHB_MASTER_HREADY ),
        .AMBA_MASTER_0_HRESP_M0     ( SERDES_IF_0_AHB_MASTER_HRESP ),
        .FIC_0_CLK                  ( PCIe_Demo_0_FIC_0_CLK ),
        .FIC_0_LOCK                 (  ),
        .SDIF_READY                 (  ),
        .SDIF0_PADDR                ( PCIe_Demo_0_SDIF0_INIT_APB_PADDR ),
        .SDIF0_PSEL                 ( PCIe_Demo_0_SDIF0_INIT_APB_PSELx ),
        .SDIF0_PENABLE              ( PCIe_Demo_0_SDIF0_INIT_APB_PENABLE ),
        .SDIF0_PWRITE               ( PCIe_Demo_0_SDIF0_INIT_APB_PWRITE ),
        .SDIF0_PWDATA               ( PCIe_Demo_0_SDIF0_INIT_APB_PWDATA ),
        .INIT_APB_S_PCLK            ( PCIe_Demo_0_INIT_APB_S_PCLK ),
        .INIT_APB_S_PRESET_N        ( PCIe_Demo_0_INIT_APB_S_PRESET_N ),
        .SDIF0_PHY_RESET_N          ( PCIe_Demo_0_SDIF0_PHY_RESET_N ),
        .SDIF0_CORE_RESET_N         ( PCIe_Demo_0_SDIF0_CORE_RESET_N ),
        .FAB_CCC_GL3                (  ),
        .MSS_READY                  ( PCIe_Demo_0_MSS_READY ),
        .GPIO_0_M2F                 ( GPIO_0_M2F_0 ),
        .GPIO_1_M2F                 ( GPIO_1_M2F_0 ),
        .GPIO_2_M2F                 ( GPIO_2_M2F_0 ),
        .GPIO_3_M2F                 ( GPIO_3_M2F_0 ),
        .GPIO_4_M2F                 ( GPIO_4_M2F_0 ),
        .GPIO_5_M2F                 ( GPIO_5_M2F_0 ),
        .GPIO_6_M2F                 ( GPIO_6_M2F_0 ),
        .GPIO_7_M2F                 ( GPIO_7_M2F_0 ) 
        );

//--------PCIe_Demo_top_SERDES_IF_0_SERDES_IF   -   Actel:SgCore:SERDES_IF:1.2.102
PCIe_Demo_top_SERDES_IF_0_SERDES_IF SERDES_IF_0(
        // Inputs
        .APB_S_PADDR      ( PCIe_Demo_0_SDIF0_INIT_APB_PADDR_0 ),
        .APB_S_PENABLE    ( PCIe_Demo_0_SDIF0_INIT_APB_PENABLE ),
        .APB_S_PSEL       ( PCIe_Demo_0_SDIF0_INIT_APB_PSELx ),
        .APB_S_PWDATA     ( PCIe_Demo_0_SDIF0_INIT_APB_PWDATA ),
        .APB_S_PWRITE     ( PCIe_Demo_0_SDIF0_INIT_APB_PWRITE ),
        .AHB_M_HREADY     ( SERDES_IF_0_AHB_MASTER_HREADY ),
        .AHB_M_HRESP      ( SERDES_IF_0_AHB_MASTER_HRESP_0 ),
        .AHB_M_HRDATA     ( SERDES_IF_0_AHB_MASTER_HRDATA ),
        .CORE_RESET_N     ( PCIe_Demo_0_SDIF0_CORE_RESET_N ),
        .PHY_RESET_N      ( PCIe_Demo_0_SDIF0_PHY_RESET_N ),
        .APB_S_PRESET_N   ( PCIe_Demo_0_INIT_APB_S_PRESET_N ),
        .CLK_BASE         ( PCIe_Demo_0_FIC_0_CLK ),
        .APB_S_PCLK       ( PCIe_Demo_0_INIT_APB_S_PCLK ),
        .PCIE_INTERRUPT   ( PCIE_INTERRUPT_net_0 ),
        .REFCLK0_P        ( REFCLK0_P ),
        .REFCLK0_N        ( REFCLK0_N ),
        .RXD0_P           ( RXD0_P ),
        .RXD0_N           ( RXD0_N ),
        .RXD1_P           ( RXD1_P ),
        .RXD1_N           ( RXD1_N ),
        .RXD2_P           ( RXD2_P ),
        .RXD2_N           ( RXD2_N ),
        .RXD3_P           ( RXD3_P ),
        .RXD3_N           ( RXD3_N ),
        // Outputs
        .APB_S_PRDATA     ( PCIe_Demo_0_SDIF0_INIT_APB_PRDATA ),
        .APB_S_PREADY     ( PCIe_Demo_0_SDIF0_INIT_APB_PREADY ),
        .APB_S_PSLVERR    ( PCIe_Demo_0_SDIF0_INIT_APB_PSLVERR ),
        .AHB_M_HADDR      ( SERDES_IF_0_AHB_MASTER_HADDR ),
        .AHB_M_HBURST     ( SERDES_IF_0_AHB_MASTER_HBURST ),
        .AHB_M_HSIZE      ( SERDES_IF_0_AHB_MASTER_HSIZE ),
        .AHB_M_HTRANS     ( SERDES_IF_0_AHB_MASTER_HTRANS ),
        .AHB_M_HWRITE     ( SERDES_IF_0_AHB_MASTER_HWRITE ),
        .AHB_M_HWDATA     ( SERDES_IF_0_AHB_MASTER_HWDATA ),
        .PCIE_SYSTEM_INT  (  ),
        .PLL_LOCK_INT     (  ),
        .PLL_LOCKLOST_INT (  ),
        .SPLL_LOCK        ( SERDES_IF_0_SPLL_LOCK ),
        .PCIE_EV_1US      (  ),
        .REFCLK0_OUT      (  ),
        .TXD0_P           ( TXD0_P_net_0 ),
        .TXD0_N           ( TXD0_N_net_0 ),
        .TXD1_P           ( TXD1_P_net_0 ),
        .TXD1_N           ( TXD1_N_net_0 ),
        .TXD2_P           ( TXD2_P_net_0 ),
        .TXD2_N           ( TXD2_N_net_0 ),
        .TXD3_P           ( TXD3_P_net_0 ),
        .TXD3_N           ( TXD3_N_net_0 ) 
        );


endmodule
