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<doc>
<title>Global Net Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.4 (Version 11.4.0.112)</text>
<text>Date: Fri Jul 18 14:10:31 2014
</text>
<section>
<name>Global Nets Information</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> GB Location </cell>
 <cell> Net Name </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>GB[4] </cell>
 <cell>(294, 72)</cell>
 <cell>PCIe_Demo_0/CCC_0/GL0_INST/U0_YWn</cell>
 <cell>124</cell>
</row>
<row>
 <cell>2</cell>
 <cell>GB[8] </cell>
 <cell>(302, 72)</cell>
 <cell>PCIe_Demo_0/PCIe_Demo_MSS_0/MSS_ADLIB_INST_RNI1A36/U0_YWn</cell>
 <cell>111</cell>
</row>
<row>
 <cell>3</cell>
 <cell>GB[3] </cell>
 <cell>(293, 72)</cell>
 <cell>PCIe_Demo_0/PCIe_Demo_MSS_0/FIC_2_APB_M_PCLK_inferred_clock_RNIPEJD/U0_YWn</cell>
 <cell>109</cell>
</row>
<row>
 <cell>4</cell>
 <cell>GB[5] </cell>
 <cell>(295, 72)</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/MSS_HPMS_READY_int_RNI3PQ3/U0_YWn_GEast</cell>
 <cell>55</cell>
</row>
<row>
 <cell>5</cell>
 <cell>GB[1] </cell>
 <cell>(291, 72)</cell>
 <cell>PCIe_Demo_0/CCC_0/GL3_INST/U0_YWn_GEast</cell>
 <cell>35</cell>
</row>
<row>
 <cell>6</cell>
 <cell>GB[6] </cell>
 <cell>(296, 72)</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm_RNIM566/U0_YWn_GEast</cell>
 <cell>33</cell>
</row>
<row>
 <cell>7</cell>
 <cell>GB[7] </cell>
 <cell>(297, 72)</cell>
 <cell>PCIe_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell>21</cell>
</row>
<row>
 <cell>8</cell>
 <cell>GB[11] </cell>
 <cell>(305, 72)</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/sm0_areset_n_clk_base_RNIEII2/U0_YWn_GEast</cell>
 <cell>21</cell>
</row>
<row>
 <cell>9</cell>
 <cell>GB[2] </cell>
 <cell>(292, 72)</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIQ516/U0_YWn_GEast</cell>
 <cell>14</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>I/O to GB Connections</name>
<text>(none)</text>
</section>
<section>
<name>Fabric to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>PCIe_Demo_0/PCIe_Demo_MSS_0/MSS_ADLIB_INST/INST_MSS_025_IP:CONFIG_PRESET_N</cell>
 <cell>(528, 146)</cell>
 <cell>GB[8] </cell>
 <cell>PCIe_Demo_0/PCIe_Demo_MSS_0/CONFIG_PRESET_N</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>PCIe_Demo_0/PCIe_Demo_MSS_0/MSS_ADLIB_INST/INST_MSS_025_IP:CLK_CONFIG_APB</cell>
 <cell>(528, 146)</cell>
 <cell>GB[3] </cell>
 <cell>PCIe_Demo_0/PCIe_Demo_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>3</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/MSS_HPMS_READY_int:Q</cell>
 <cell>(576, 58)</cell>
 <cell>GB[5] </cell>
 <cell>PCIe_Demo_0/CORERESETP_0/MSS_HPMS_READY_int</cell>
 <cell>ROUTED</cell>
 <cell>6</cell>
</row>
<row>
 <cell>4</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/genblk2_sdif0_phr/reset_n_clk_ltssm:Q</cell>
 <cell>(422, 61)</cell>
 <cell>GB[6] </cell>
 <cell>PCIe_Demo_0/CORERESETP_0/genblk2.sdif0_phr/reset_n_clk_ltssm</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>5</cell>
 <cell>PCIe_Demo_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>(25, 134)</cell>
 <cell>GB[7] </cell>
 <cell>PCIe_Demo_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>6</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/sm0_areset_n_clk_base:Q</cell>
 <cell>(586, 88)</cell>
 <cell>GB[11] </cell>
 <cell>PCIe_Demo_0/CORERESETP_0/sm0_areset_n_clk_base</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>7</cell>
 <cell>PCIe_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>(579, 79)</cell>
 <cell>GB[2] </cell>
 <cell>PCIe_Demo_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC to GB Connections</name>
<table>
<header>
 <cell/>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell>Pin Swapped for Back Annotation Only</cell>
 <cell> To </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>PCIe_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>CCC-SW0 (0, 11)</cell>
 <cell>None</cell>
 <cell>GB[4] </cell>
 <cell>PCIe_Demo_0/CCC_0/GL0_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
<row>
 <cell>2</cell>
 <cell>PCIe_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:GL3</cell>
 <cell>CCC-SW0 (0, 11)</cell>
 <cell>GL3 =&gt; GL1</cell>
 <cell>GB[1] </cell>
 <cell>PCIe_Demo_0/CCC_0/GL3_net</cell>
 <cell>HARDWIRED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>CCC Input Connections</name>
<table>
<header>
 <cell/>
 <cell> Port Name </cell>
 <cell> Pin Number </cell>
 <cell> I/O Function </cell>
 <cell> From </cell>
 <cell> From Location </cell>
 <cell> To </cell>
 <cell> CCC Location </cell>
 <cell> Net Name </cell>
 <cell> Net Type </cell>
 <cell> Fanout </cell>
</header>
<row>
 <cell>1</cell>
 <cell>CLK0</cell>
 <cell>K1</cell>
 <cell>MSIOD103PB6/CCC_SW0_CLKI0</cell>
 <cell>CLK0_ibuf/U0/U_IOIN:Y</cell>
 <cell>West IO #0 (0, 52)</cell>
 <cell>PCIe_Demo_0/CCC_0/CCC_INST/INST_CCC_IP:CLK0</cell>
 <cell>CCC-SW0 (0, 11)</cell>
 <cell>CLK0_c</cell>
 <cell>ROUTED</cell>
 <cell>1</cell>
</row>
</table>
<text></text>
</section>
<section>
<name>Local Clock Nets to RGB Connections</name>
<text>(none)</text>
</section>
</doc>
