Project Settings
Project Name M2S_SOM_syn Implementation Name synthesis
Top Module M2S_SOM Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
Compile InputComplete 33 9 0 - 0m:01s - 14.04.2014
13:11:15
Pre-mappingComplete 14 7 0 0m:00s 0m:00s 135MB 14.04.2014
13:11:18
Map & OptimizeComplete 32 26 0 0m:01s 0m:01s 135MB 14.04.2014
13:11:20

Area Summary
Carry Cells 14 Sequential Cells 91
DSP Blocks (MACC) (dsp_used) 0 I/O Cells 87
Global Clock Buffers 5 LUTs (total_luts) 69

Timing Summary
Clock NameReq FreqEst FreqSlack
50_MHz_RC_Clock50.0 MHz349.7 MHz17.141
FIC_2_APB_M_PCLK_inferred_clock41.5 MHz141.8 MHz8.791
GL0_net_inferred_clock83.0 MHzNANA
MAC_MII_RX_CLK25.0 MHzNANA
MAC_MII_TX_CLK25.0 MHzNANA
System100.0 MHz895.2 MHz8.883

Optimizations Summary
Combined Clock Conversion 5 / 0