Project Settings |
---|
Project Name | M2S_SOM_syn | Implementation Name | synthesis |
Top Module | M2S_SOM | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 10000 |
Disable I/O Insertion | 0 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
Compile Input | Complete |
33 |
9 |
0 |
- |
0m:01s |
- |
14.04.2014 13:11:15 |
Pre-mapping | Complete |
14 |
7 |
0 |
0m:00s |
0m:00s |
135MB |
14.04.2014 13:11:18 |
Map & Optimize | Complete |
32 |
26 |
0 |
0m:01s |
0m:01s |
135MB |
14.04.2014 13:11:20 |
Area Summary |
|
Carry Cells | 14 |
Sequential Cells | 91 |
DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 87 |
Global Clock Buffers | 5 |
LUTs
(total_luts) | 69 |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
50_MHz_RC_Clock | 50.0 MHz | 349.7 MHz | 17.141 |
FIC_2_APB_M_PCLK_inferred_clock | 41.5 MHz | 141.8 MHz | 8.791 |
GL0_net_inferred_clock | 83.0 MHz | NA | NA |
MAC_MII_RX_CLK | 25.0 MHz | NA | NA |
MAC_MII_TX_CLK | 25.0 MHz | NA | NA |
System | 100.0 MHz | 895.2 MHz | 8.883 |
Optimizations Summary |
Combined Clock Conversion | 5 / 0 |
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