#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.2 #Hostname: I7 #Implementation: synthesis $ Start of Compile #Mon Apr 14 13:11:14 2014 Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_pipes.svh" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\hypermods.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\Actel\DirectCore\CoreSF2Config\3.0.100\rtl\vlog\core\coresf2config.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM\FCCC_0\M2S_SOM_FCCC_0_FCCC.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM_MSS\M2S_SOM_MSS_syn.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM_MSS\M2S_SOM_MSS.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\Actel\SgCore\OSC\1.0.100\osc_comps.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM\OSC_0\M2S_SOM_OSC_0_OSC.v" @I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM\M2S_SOM.v" Verilog syntax check successful! Selecting top level module M2S_SOM @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF @N:CG364 : coresf2config.v(21) | Synthesizing module CoreSF2Config @N:CG364 : coresf2reset.v(22) | Synthesizing module CoreSF2Reset FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000011 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 COUNT_130us=32'b00000000000000000001100101100100 COUNT_DDR=32'b00000000000000000010011100010000 COUNT_MAX=32'b00000000000000000010011100010000 COUNT_WIDTH=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreSF2Reset_Z1 @N:CL177 : coresf2reset.v(659) | Sharing sequential element M3_RESET_N. @N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coresf2reset.v(421) | Sharing sequential element fpll_lock_q1. @N:CG364 : smartfusion2.v(371) | Synthesizing module VCC @N:CG364 : smartfusion2.v(367) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(722) | Synthesizing module CCC @N:CG364 : M2S_SOM_FCCC_0_FCCC.v(5) | Synthesizing module M2S_SOM_FCCC_0_FCCC @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : M2S_SOM_MSS_syn.v(5) | Synthesizing module MSS_050 @N:CG364 : M2S_SOM_MSS.v(9) | Synthesizing module M2S_SOM_MSS @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : osc_comps.v(23) | Synthesizing module XTLOSC @N:CG364 : M2S_SOM_OSC_0_OSC.v(5) | Synthesizing module M2S_SOM_OSC_0_OSC @N:CG364 : smartfusion2.v(713) | Synthesizing module SYSRESET @N:CG364 : M2S_SOM.v(9) | Synthesizing module M2S_SOM @W:CL157 : M2S_SOM_OSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : M2S_SOM_OSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : M2S_SOM_OSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : M2S_SOM_OSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @N:CL177 : coresf2reset.v(421) | Sharing sequential element fpll_lock_q2. @N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif2_spll_lock_q2. @N:CL201 : coresf2reset.v(704) | Trying to extract state machine for register sm2_state Extracted state machine for register sm2_state State machine has 2 reachable states with original encodings of: 000 001 @N:CL201 : coresf2reset.v(550) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coresf2reset.v(49) | Input FPLL_LOCK is unused @W:CL159 : coresf2reset.v(52) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coresf2reset.v(56) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coresf2reset.v(60) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coresf2reset.v(64) | Input SDIF3_SPLL_LOCK is unused @N:CL201 : coresf2config.v(323) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @END At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Apr 14 13:11:15 2014 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Reading constraint file: C:\Actelprj\m2s050-som-fg484-1a\constraint\M2S_SOM_FG484_TOP_synthesis.sdc Linked File: M2S_SOM_scck.rpt Printing clock summary report in "C:\Actelprj\m2s050-som-fg484-1a\synthesis\M2S_SOM_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 104MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.MDDR_DDR_AXI_S_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.FDDR_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF3_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF2_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF2_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF1_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF1_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF0_CORE_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF3_PHY_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF2_PHY_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF2_PHY_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF1_PHY_RESET_N @W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF1_PHY_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF0_PHY_RESET_N @N:BN362 : coresf2config.v(337) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(659) | Removing sequential instance MSS_RESET_N_F2M_1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(550) | Removing sequential instance FDDR_CORE_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(550) | Removing sequential instance SDIF0_PHY_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(550) | Removing sequential instance SDIF0_CORE_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(356) | Removing sequential instance sm1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs @N:BN362 : coresf2reset.v(356) | Removing sequential instance sm1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=69 set on top level netlist M2S_SOM Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------ 50_MHz_RC_Clock 50.0 MHz 20.000 declared Inferred_clkgroup_1 FIC_2_APB_M_PCLK_inferred_clock 41.5 MHz 24.096 declared Inferred_clkgroup_2 GL0_net_inferred_clock 83.0 MHz 12.048 declared Inferred_clkgroup_0 MAC_MII_RX_CLK 25.0 MHz 40.000 declared MAC_Clocks MAC_MII_TX_CLK 25.0 MHz 40.000 declared MAC_Clocks System 1.0 MHz 1000.000 system system_clkgroup ================================================================================================ Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Actelprj\m2s050-som-fg484-1a\synthesis\M2S_SOM.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Apr 14 13:11:18 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) @W:MO111 : m2s_som_osc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module M2S_SOM_OSC_0_OSC) @W:MO111 : m2s_som_osc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module M2S_SOM_OSC_0_OSC) @W:MO111 : m2s_som_osc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module M2S_SOM_OSC_0_OSC) @W:MO111 : m2s_som_osc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module M2S_SOM_OSC_0_OSC) @W:BN132 : coresf2reset.v(370) | Removing sequential instance CoreSF2Reset_0.sm2_areset_n_q1, because it is equivalent to instance CoreSF2Reset_0.sm0_areset_n_q1 @W:BN132 : coresf2reset.v(370) | Removing sequential instance CoreSF2Reset_0.sm2_areset_n_rcosc, because it is equivalent to instance CoreSF2Reset_0.sm0_areset_n_rcosc Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB) Encoding state machine state[2:0] (view:work.CoreSF2Config(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[17] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[18] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[19] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[20] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[21] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[22] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[23] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[24] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[25] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[26] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[27] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[28] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[29] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[30] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[31] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance paddr[11] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[31], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[30] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[30], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[29] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[29], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[28] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[28], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[27] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[27], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[26] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[26], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[25] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[25], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[24] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[24], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[23] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[23], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[22] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[22], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[21] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[21], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[20] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[20], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[19] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[19], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[18] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[18], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[17] @W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[17], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[16] @N:BN362 : coresf2config.v(422) | Removing sequential instance FIC_2_APB_M_PRDATA[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs @N:BN362 : coresf2config.v(150) | Removing sequential instance paddr[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs Encoding state machine sm0_state[6:0] (view:work.CoreSF2Reset_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine sm2_state[1:0] (view:work.CoreSF2Reset_Z1(verilog)) original code -> new code 000 -> 0 001 -> 1 @N: : coresf2reset.v(722) | Found counter in view:work.CoreSF2Reset_Z1(verilog) inst count[13:0] @W:BN132 : coresf2reset.v(421) | Removing sequential instance CoreSF2Reset_0.sdif3_spll_lock_q1, because it is equivalent to instance CoreSF2Reset_0.sm2_state[0] @W:BN132 : coresf2reset.v(550) | Removing instance CoreSF2Reset_0.USER_FAB_RESET_N, because it is equivalent to instance CoreSF2Reset_0.sm0_state[6] @N:BN362 : coresf2config.v(150) | Removing sequential instance CoreSF2Config_0.paddr[14] in hierarchy view:work.M2S_SOM(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.88ns 104 / 91 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.88ns 103 / 91 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.88ns 103 / 91 ------------------------------------------------------------ @N:FP130 : | Promoting Net OSC_0_RCOSC_25_50MHZ_O2F on CLKINT I_6 @N:FP130 : | Promoting Net CoreSF2Reset_0.sm2_areset_n_rcosc on CLKINT I_7 @N:FP130 : | Promoting Net CoreSF2Config_0_APB_S_PRESET_N on CLKINT I_8 @N:FP130 : | Promoting Net CoreSF2Config_0_APB_S_PCLK on CLKINT I_9 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 134MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 5 non-gated/non-generated clock tree(s) driving 95 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================================ Non-Gated/Non-Generated Clocks ============================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------------ ClockId0001 FCCC_0.GL0_INST CLKINT 1 M2S_SOM_MSS_0.MSS_ADLIB_INST ClockId0002 M2S_SOM_MSS_0.FIC_2_APB_M_PCLK_keep keepbuf 57 M2S_SOM_MSS_0.MSS_ADLIB_INST ClockId0003 OSC_0.RCOSC_25_50MHZ_O2F_keep keepbuf 35 CoreSF2Reset_0.count[13] ClockId0004 MAC_MII_TX_CLK port 1 M2S_SOM_MSS_0.MSS_ADLIB_INST ClockId0005 MAC_MII_RX_CLK port 1 M2S_SOM_MSS_0.MSS_ADLIB_INST ======================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\Actelprj\m2s050-som-fg484-1a\synthesis\M2S_SOM.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 132MB peak: 134MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 133MB peak: 135MB) @W:MT246 : m2s_som.v(563) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : m2s_som_osc_0_osc.v(28) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : m2s_som_fccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) Found clock MAC_MII_RX_CLK with period 40.00ns Found clock MAC_MII_TX_CLK with period 40.00ns Found clock 50_MHz_RC_Clock with period 20.00ns Found clock FIC_2_APB_M_PCLK_inferred_clock with period 24.10ns Found clock GL0_net_inferred_clock with period 12.05ns ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Apr 14 13:11:20 2014 # Top view: M2S_SOM Requested Frequency: 25.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\Actelprj\m2s050-som-fg484-1a\constraint\M2S_SOM_FG484_TOP_synthesis.sdc @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 8.791 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------- 50_MHz_RC_Clock 50.0 MHz 349.7 MHz 20.000 2.859 17.141 declared Inferred_clkgroup_1 FIC_2_APB_M_PCLK_inferred_clock 41.5 MHz 141.8 MHz 24.096 7.051 8.791 declared Inferred_clkgroup_2 GL0_net_inferred_clock 83.0 MHz NA 12.048 NA NA declared Inferred_clkgroup_0 MAC_MII_RX_CLK 25.0 MHz NA 40.000 NA NA declared MAC_Clocks MAC_MII_TX_CLK 25.0 MHz NA 40.000 NA NA declared MAC_Clocks System 100.0 MHz 895.2 MHz 10.000 1.117 8.883 system system_clkgroup ======================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 8.883 | No paths - | No paths - | No paths - 50_MHz_RC_Clock 50_MHz_RC_Clock | 20.000 17.141 | No paths - | No paths - | No paths - 50_MHz_RC_Clock FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - FIC_2_APB_M_PCLK_inferred_clock 50_MHz_RC_Clock | Diff grp - | No paths - | No paths - | No paths - FIC_2_APB_M_PCLK_inferred_clock FIC_2_APB_M_PCLK_inferred_clock | 24.096 17.045 | No paths - | 12.048 9.589 | 12.048 8.791 ========================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: 50_MHz_RC_Clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------- CoreSF2Reset_0.count[0] 50_MHz_RC_Clock SLE Q count[0] 0.087 17.141 CoreSF2Reset_0.count[1] 50_MHz_RC_Clock SLE Q count[1] 0.108 17.333 CoreSF2Reset_0.count[2] 50_MHz_RC_Clock SLE Q count[2] 0.108 17.350 CoreSF2Reset_0.count[3] 50_MHz_RC_Clock SLE Q count[3] 0.108 17.366 CoreSF2Reset_0.count[4] 50_MHz_RC_Clock SLE Q count[4] 0.108 17.382 CoreSF2Reset_0.count[5] 50_MHz_RC_Clock SLE Q count[5] 0.108 17.398 CoreSF2Reset_0.sm0_state[5] 50_MHz_RC_Clock SLE Q sm0_state[5] 0.108 17.409 CoreSF2Reset_0.count[6] 50_MHz_RC_Clock SLE Q count[6] 0.108 17.415 CoreSF2Reset_0.count[7] 50_MHz_RC_Clock SLE Q count[7] 0.108 17.431 CoreSF2Reset_0.count[8] 50_MHz_RC_Clock SLE Q count[8] 0.108 17.447 ======================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------- CoreSF2Reset_0.count_130us 50_MHz_RC_Clock SLE EN count_130us4 19.663 17.141 CoreSF2Reset_0.count_ddr 50_MHz_RC_Clock SLE EN count_ddr4 19.663 17.141 CoreSF2Reset_0.count[13] 50_MHz_RC_Clock SLE D count_s[13] 19.745 17.272 CoreSF2Reset_0.count[12] 50_MHz_RC_Clock SLE D count_s[12] 19.745 17.288 CoreSF2Reset_0.count[11] 50_MHz_RC_Clock SLE D count_s[11] 19.745 17.305 CoreSF2Reset_0.count[10] 50_MHz_RC_Clock SLE D count_s[10] 19.745 17.321 CoreSF2Reset_0.count[9] 50_MHz_RC_Clock SLE D count_s[9] 19.745 17.337 CoreSF2Reset_0.count[8] 50_MHz_RC_Clock SLE D count_s[8] 19.745 17.354 CoreSF2Reset_0.count[7] 50_MHz_RC_Clock SLE D count_s[7] 19.745 17.370 CoreSF2Reset_0.count[6] 50_MHz_RC_Clock SLE D count_s[6] 19.745 17.386 ======================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.337 + Clock delay at ending point: 0.000 (ideal) = Required time: 19.663 - Propagation time: 2.522 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 17.141 Number of logic level(s): 2 Starting point: CoreSF2Reset_0.count[0] / Q Ending point: CoreSF2Reset_0.count_130us / EN The start point is clocked by 50_MHz_RC_Clock [rising] on pin CLK The end point is clocked by 50_MHz_RC_Clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- CoreSF2Reset_0.count[0] SLE Q Out 0.087 0.087 - count[0] Net - - 0.778 - 4 CoreSF2Reset_0.count_130us4_9 CFG4 D In - 0.865 - CoreSF2Reset_0.count_130us4_9 CFG4 Y Out 0.472 1.338 - count_130us4_9 Net - - 0.556 - 1 CoreSF2Reset_0.count_130us4 CFG4 D In - 1.893 - CoreSF2Reset_0.count_130us4 CFG4 Y Out 0.470 2.363 - count_130us4 Net - - 0.159 - 1 CoreSF2Reset_0.count_130us SLE EN In - 2.522 - ============================================================================================ Total path delay (propagation time + setup) of 2.859 is 1.367(47.8%) logic and 1.492(52.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreSF2Config_0.psel FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.108 8.791 CoreSF2Config_0.state[1] FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.087 9.589 CoreSF2Config_0.MDDR_PENABLE FIC_2_APB_M_PCLK_inferred_clock SLE Q CoreSF2Config_0_MDDR_APBmslave_PENABLE 0.108 10.154 CoreSF2Config_0.paddr[13] FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[13] 0.108 10.518 CoreSF2Config_0.paddr[15] FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[15] 0.108 10.595 CoreSF2Config_0.state[0] FIC_2_APB_M_PCLK_inferred_clock SLE Q state[0] 0.087 10.604 CoreSF2Config_0.paddr[12] FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[12] 0.108 10.749 M2S_SOM_MSS_0.MSS_ADLIB_INST FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[3] CoreSF2Config_0_MDDR_APBmslave_PRDATA[3] 5.356 17.045 M2S_SOM_MSS_0.MSS_ADLIB_INST FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[0] CoreSF2Config_0_MDDR_APBmslave_PRDATA[0] 4.996 17.141 M2S_SOM_MSS_0.MSS_ADLIB_INST FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[5] CoreSF2Config_0_MDDR_APBmslave_PRDATA[5] 5.180 17.221 ========================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreSF2Config_0.state[1] FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 11.873 8.791 M2S_SOM_MSS_0.MSS_ADLIB_INST FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PSEL CoreSF2Config_0_MDDR_APBmslave_PSELx 11.338 8.885 CoreSF2Config_0.FIC_2_APB_M_PREADY FIC_2_APB_M_PCLK_inferred_clock SLE EN N_11_i_0 11.711 9.018 CoreSF2Config_0.control_reg_2 FIC_2_APB_M_PCLK_inferred_clock SLE EN N_7 11.711 9.035 CoreSF2Config_0.FIC_2_APB_M_PRDATA[0] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 11.793 9.079 CoreSF2Config_0.FIC_2_APB_M_PRDATA[1] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[1] 11.793 9.166 CoreSF2Config_0.FIC_2_APB_M_PRDATA[2] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 11.793 9.166 CoreSF2Config_0.FIC_2_APB_M_PRDATA[3] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 11.793 9.166 CoreSF2Config_0.FIC_2_APB_M_PRDATA[4] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 11.793 9.166 CoreSF2Config_0.FIC_2_APB_M_PRDATA[5] FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 11.793 9.166 ========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.048 - Setup time: 0.175 + Clock delay at ending point: 0.000 (ideal) = Required time: 11.873 - Propagation time: 3.082 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 8.791 Number of logic level(s): 2 Starting point: CoreSF2Config_0.psel / Q Ending point: CoreSF2Config_0.state[1] / D The start point is clocked by FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- CoreSF2Config_0.psel SLE Q Out 0.108 0.108 - psel Net - - 0.733 - 3 CoreSF2Config_0.MDDR_PSEL_0_a2 CFG4 D In - 0.841 - CoreSF2Config_0.MDDR_PSEL_0_a2 CFG4 Y Out 0.470 1.311 - CoreSF2Config_0_MDDR_APBmslave_PSELx Net - - 1.143 - 20 CoreSF2Config_0.state_ns_0_0[1] CFG4 D In - 2.454 - CoreSF2Config_0.state_ns_0_0[1] CFG4 Y Out 0.470 2.923 - state_ns[1] Net - - 0.159 - 1 CoreSF2Config_0.state[1] SLE D In - 3.082 - =================================================================================================== Total path delay (propagation time + setup) of 3.257 is 1.223(37.5%) logic and 2.034(62.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------ OSC_0.I_XTLOSC System XTLOSC CLKOUT OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 0.000 8.883 ============================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------ FCCC_0.CCC_INST System CCC XTLOSC OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 10.000 8.883 ============================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 1.117 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 8.883 Number of logic level(s): 0 Starting point: OSC_0.I_XTLOSC / CLKOUT Ending point: FCCC_0.CCC_INST / XTLOSC The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------- OSC_0.I_XTLOSC XTLOSC CLKOUT Out 0.000 0.000 - OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC Net - - 1.117 - 1 FCCC_0.CCC_INST CCC XTLOSC In - 1.117 - ================================================================================================== Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for M2S_SOM Mapping to part: m2s050tfbga484std Cell usage: CCC 1 use CLKINT 5 uses MSS_050 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use XTLOSC 1 use CFG1 2 uses CFG2 26 uses CFG3 9 uses CFG4 18 uses Carry primitives used for arithmetic functions: ARI1 14 uses Sequential Cells: SLE 91 uses DSP Blocks: 0 I/O ports: 90 I/O primitives: 87 BIBUF 29 uses INBUF 16 uses OUTBUF 37 uses OUTBUF_DIFF 1 use TRIBUFF 4 uses Global Clock Buffers: 5 Total LUTs: 69 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Apr 14 13:11:20 2014 ###########################################################]