Synopsys Verilog Compiler, version comp201303rcp1, Build 114R, built May 21 2013
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\generic\smartfusion2.v"
@I::"C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\vlog\umr_capim.v"
@I::"C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\vlog\scemi_pipes.svh"
@I::"C:\Microsemi\Libero_v11.1\Synopsys\synplify_H201303M1\lib\vlog\hypermods.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\Actel\DirectCore\CoreSF2Config\3.0.100\rtl\vlog\core\coresf2config.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\Actel\DirectCore\CoreSF2Reset\3.0.100\rtl\vlog\core\coresf2reset.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM\FCCC_0\M2S_SOM_FCCC_0_FCCC.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM_MSS\M2S_SOM_MSS_tmp_syn.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM_MSS\M2S_SOM_MSS.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\Actel\SgCore\OSC\1.0.100\osc_comps.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM\OSC_0\M2S_SOM_OSC_0_OSC.v"
@I::"C:\Actelprj\m2s050-som-fg484-1a\component\work\M2S_SOM\M2S_SOM.v"
Verilog syntax check successful!
Selecting top level module M2S_SOM
@N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF

@N:CG364 : coresf2config.v(21) | Synthesizing module CoreSF2Config

@N:CG364 : coresf2reset.v(22) | Synthesizing module CoreSF2Reset

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000011
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	SDIF2_IN_USE=32'b00000000000000000000000000000000
	SDIF3_IN_USE=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	COUNT_130us=32'b00000000000000000001100101100100
	COUNT_DDR=32'b00000000000000000010011100010000
	COUNT_MAX=32'b00000000000000000010011100010000
	COUNT_WIDTH=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreSF2Reset_Z1

@N:CL177 : coresf2reset.v(659) | Sharing sequential element M3_RESET_N.
@N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif2_spll_lock_q1.
@N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif1_spll_lock_q1.
@N:CL177 : coresf2reset.v(421) | Sharing sequential element sdif0_spll_lock_q1.
@N:CL177 : coresf2reset.v(421) | Sharing sequential element fpll_lock_q1.
@N:CG364 : smartfusion2.v(371) | Synthesizing module VCC

@N:CG364 : smartfusion2.v(367) | Synthesizing module GND

@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

@N:CG364 : smartfusion2.v(722) | Synthesizing module CCC

@N:CG364 : M2S_SOM_FCCC_0_FCCC.v(5) | Synthesizing module M2S_SOM_FCCC_0_FCCC

@N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF

@N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF

@N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

@N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

@N:CG364 : M2S_SOM_MSS_tmp_syn.v(5) | Synthesizing module MSS_050

@N:CG364 : M2S_SOM_MSS.v(9) | Synthesizing module M2S_SOM_MSS

@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

@N:CG364 : osc_comps.v(23) | Synthesizing module XTLOSC

@N:CG364 : M2S_SOM_OSC_0_OSC.v(5) | Synthesizing module M2S_SOM_OSC_0_OSC

@N:CG364 : smartfusion2.v(713) | Synthesizing module SYSRESET

@N:CG364 : M2S_SOM.v(9) | Synthesizing module M2S_SOM

@END

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 38MB peak: 40MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jun 25 18:05:24 2013

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