ic Technology Pre-mapping, Version mapact, Build 976R, Built May 23 2013 12:10:32
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version H-2013.03M-1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)
Linked File: M2S_SOM_scck.rpt
Printing clock summary report in "C:\Actelprj\m2s050-som-fg484-1a\synthesis\M2S_SOM_scck.rpt" file
@N:MF249 : | Running in 32-bit mode.
@N:MF667 : | Clock conversion disabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 60MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 62MB)
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.MDDR_DDR_AXI_S_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.FDDR_CORE_RESET_N
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF3_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF2_CORE_RESET_N
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF2_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF1_CORE_RESET_N
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF1_CORE_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF0_CORE_RESET_N
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF3_PHY_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF2_PHY_RESET_N
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF2_PHY_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF1_PHY_RESET_N
@W:BN132 : coresf2reset.v(550) | Removing sequential instance CoreSF2Reset_0.SDIF1_PHY_RESET_N, because it is equivalent to instance CoreSF2Reset_0.SDIF0_PHY_RESET_N
@N:BN362 : coresf2config.v(337) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(337) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2reset.v(659) | Removing sequential instance MSS_RESET_N_F2M_1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs
@N:BN362 : coresf2reset.v(550) | Removing sequential instance FDDR_CORE_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs
@N:BN362 : coresf2reset.v(550) | Removing sequential instance SDIF0_PHY_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs
@N:BN362 : coresf2reset.v(550) | Removing sequential instance SDIF0_CORE_RESET_N of view:PrimLib.dffre(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs
@N:BN362 : coresf2reset.v(356) | Removing sequential instance sm1_areset_n_rcosc of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs
@N:BN362 : coresf2reset.v(356) | Removing sequential instance sm1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs
syn_allowed_resources : blockrams=69 set on top level netlist M2S_SOM
Clock Summary
**************
Start Requested Requested Clock Clock
Clock Frequency Period Type Group
--------------------------------------------------------------------------------------------------------------------
System 1.0 MHz 1000.000 system system_clkgroup
M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0
M2S_SOM|MAC_MII_TX_CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_1
M2S_SOM|MAC_MII_RX_CLK 100.0 MHz 10.000 inferred Inferred_clkgroup_2
M2S_SOM_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3
M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_4
====================================================================================================================
@W:MT530 : coresf2config.v(323) | Found inferred clock M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 92 sequential elements including CoreSF2Config_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance.
@W:MT530 : m2s_som_mss.v(1472) | Found inferred clock M2S_SOM|MAC_MII_TX_CLK which controls 0 sequential elements including M2S_SOM_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance.
@W:MT530 : m2s_som_mss.v(1472) | Found inferred clock M2S_SOM|MAC_MII_RX_CLK which controls 0 sequential elements including M2S_SOM_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance.
@W:MT530 : m2s_som_mss.v(1472) | Found inferred clock M2S_SOM_FCCC_0_FCCC|GL0_net_inferred_clock which controls 0 sequential elements including M2S_SOM_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance.
@W:MT530 : coresf2reset.v(722) | Found inferred clock M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock which controls 40 sequential elements including CoreSF2Reset_0.count[13:0]. This clock has no specified timing constraint which may adversely impact design performance.
Finished Pre Mapping Phase.@N: BN225 |Writing default property annotation file C:\Actelprj\m2s050-som-fg484-1a\synthesis\M2S_SOM.sap.
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 80MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jun 25 17:08:00 2013
###########################################################]
Map & Optimize Report
Synopsys Generic Technology Mapper, Version mapact, Build 976R, Built May 23 2013 12:10:32
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version H-2013.03M-1
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB)
@N:MF249 : | Running in 32-bit mode.
@N:MF667 : | Clock conversion disabled
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 58MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 58MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 59MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)
@W:MO111 : m2s_som_osc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module M2S_SOM_OSC_0_OSC)
@W:MO111 : m2s_som_osc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module M2S_SOM_OSC_0_OSC)
@W:MO111 : m2s_som_osc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module M2S_SOM_OSC_0_OSC)
@W:MO111 : m2s_som_osc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module M2S_SOM_OSC_0_OSC)
@W:BN132 : coresf2reset.v(370) | Removing sequential instance CoreSF2Reset_0.sm2_areset_n_q1, because it is equivalent to instance CoreSF2Reset_0.sm0_areset_n_q1
@W:BN132 : coresf2reset.v(370) | Removing sequential instance CoreSF2Reset_0.sm2_areset_n_rcosc, because it is equivalent to instance CoreSF2Reset_0.sm0_areset_n_rcosc
Available hyper_sources - for debug and ip models
None Found
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)
Encoding state machine state[2:0] (view:work.CoreSF2Config(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[17] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[18] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[19] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[20] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[21] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[22] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[23] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[24] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[25] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[26] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[27] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[28] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[29] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[30] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance pwdata[31] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance paddr[11] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[31], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[30]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[30], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[29]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[29], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[28]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[28], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[27]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[27], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[26]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[26], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[25]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[25], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[24]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[24], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[23]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[23], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[22]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[22], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[21]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[21], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[20]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[20], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[19]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[19], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[18]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[18], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[17]
@W:BN132 : coresf2config.v(422) | Removing instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[17], because it is equivalent to instance CoreSF2Config_0.FIC_2_APB_M_PRDATA[16]
@N:BN362 : coresf2config.v(422) | Removing sequential instance FIC_2_APB_M_PRDATA[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
@N:BN362 : coresf2config.v(150) | Removing sequential instance paddr[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs
Encoding state machine sm0_state[6:0] (view:work.CoreSF2Reset_Z1(verilog))
original code -> new code
000 -> 0000001
001 -> 0000010
010 -> 0000100
011 -> 0001000
100 -> 0010000
101 -> 0100000
110 -> 1000000
Encoding state machine sm2_state[1:0] (view:work.CoreSF2Reset_Z1(verilog))
original code -> new code
000 -> 0
001 -> 1
@N: : coresf2reset.v(722) | Found counter in view:work.CoreSF2Reset_Z1(verilog) inst count[13:0]
@W:BN132 : coresf2reset.v(421) | Removing sequential instance CoreSF2Reset_0.sdif3_spll_lock_q1, because it is equivalent to instance CoreSF2Reset_0.sm2_state[0]
@W:BN132 : coresf2reset.v(550) | Removing instance CoreSF2Reset_0.USER_FAB_RESET_N, because it is equivalent to instance CoreSF2Reset_0.sm0_state[6]
@N:BN362 : coresf2config.v(150) | Removing sequential instance CoreSF2Config_0.paddr[14] in hierarchy view:work.M2S_SOM(verilog) because there are no references to its outputs
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -6.85ns 106 / 91
2 0h:00m:00s -6.89ns 108 / 91
------------------------------------------------------------
@N:FX271 : coresf2reset.v(722) | Instance "CoreSF2Reset_0.count[1]" with 4 loads replicated 1 times to improve timing
@N:FX271 : coresf2reset.v(722) | Instance "CoreSF2Reset_0.count[0]" with 5 loads replicated 1 times to improve timing
Timing driven replication report
Added 2 Registers via timing driven replication
Added 1 LUTs via timing driven replication
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -1.00ns 112 / 93
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -1.00ns 112 / 93
------------------------------------------------------------
@N:FP130 : | Promoting Net M2S_SOM_MSS_0.FIC_2_APB_M_PCLK_i on CLKINT I_9
@N:FP130 : | Promoting Net OSC_0.RCOSC_25_50MHZ_O2F_i on CLKINT I_10
@N:FP130 : | Promoting Net CoreSF2Config_0_APB_S_PRESET_N on CLKINT I_11
@N:FP130 : | Promoting Net CoreSF2Reset_0.sm2_areset_n_rcosc on CLKINT I_12
Added 0 Buffers
Added 0 Cells via replication
Added 0 Sequential Cells via replication
Added 0 Combinational Cells via replication
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 79MB)
#### START OF CLOCK OPTIMIZATION REPORT #####[
Clock optimization not enabled
3 non-gated/non-generated clock tree(s) driving 3 clock pin(s) of sequential element(s)
2 gated/generated clock tree(s) driving 94 clock pin(s) of sequential element(s)
0 instances converted, 94 sequential instances remain driven by gated/generated clocks
================================== Non-Gated/Non-Generated Clocks ==================================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
----------------------------------------------------------------------------------------------------
ClockId0003 MAC_MII_TX_CLK port 1 M2S_SOM_MSS_0.MSS_ADLIB_INST
ClockId0004 MAC_MII_RX_CLK port 1 M2S_SOM_MSS_0.MSS_ADLIB_INST
ClockId0005 FCCC_0.GL0_INST CLKINT 1 M2S_SOM_MSS_0.MSS_ADLIB_INST
====================================================================================================
============================================================================================================== Gated/Generated Clocks ==============================================================================================================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001 M2S_SOM_MSS_0.MSS_ADLIB_INST MSS_050 57 M2S_SOM_MSS_0.MSS_ADLIB_INST No generated or derived clock directive on output of sequential instance
ClockId0002 OSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ 37 CoreSF2Reset_0.count_fast[0] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
====================================================================================================================================================================================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Writing Analyst data base C:\Actelprj\m2s050-som-fg484-1a\synthesis\M2S_SOM.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 79MB)
Writing EDIF Netlist and constraint files
H-2013.03M-1
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 78MB peak: 79MB)
@W:MT246 : m2s_som.v(563) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : m2s_som_osc_0_osc.v(28) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : m2s_som_osc_0_osc.v(24) | Blackbox RCOSC_25_50MHZ_FAB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : m2s_som_fccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT420 : | Found inferred clock M2S_SOM|MAC_MII_RX_CLK with period 10.00ns. Please declare a user-defined clock on object "p:MAC_MII_RX_CLK"
@W:MT420 : | Found inferred clock M2S_SOM|MAC_MII_TX_CLK with period 10.00ns. Please declare a user-defined clock on object "p:MAC_MII_TX_CLK"
@W:MT420 : | Found inferred clock M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:OSC_0.RCOSC_25_50MHZ_O2F"
@W:MT420 : | Found inferred clock M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:M2S_SOM_MSS_0.FIC_2_APB_M_PCLK"
@W:MT420 : | Found inferred clock M2S_SOM_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net"
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jun 25 17:08:02 2013
#
Top view: M2S_SOM
Requested Frequency: 100.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.
Performance Summary
*******************
Worst slack in design: 1.788
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------------------------------
M2S_SOM_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_3
M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 141.4 MHz 10.000 7.073 1.788 inferred Inferred_clkgroup_0
M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock 100.0 MHz 342.7 MHz 10.000 2.918 7.082 inferred Inferred_clkgroup_4
M2S_SOM|MAC_MII_RX_CLK 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_2
M2S_SOM|MAC_MII_TX_CLK 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1
System 100.0 MHz 895.2 MHz 10.000 1.117 8.883 system system_clkgroup
==========================================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System System | 10.000 8.883 | No paths - | No paths - | No paths -
M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 2.927 | No paths - | 5.000 2.551 | 5.000 1.788
M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock | 10.000 7.082 | No paths - | No paths - | No paths -
================================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CoreSF2Config_0.psel M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.108 1.788
CoreSF2Config_0.state[1] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.087 2.551
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[3] CoreSF2Config_0_MDDR_APBmslave_PRDATA[3] 5.465 2.927
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[0] CoreSF2Config_0_MDDR_APBmslave_PRDATA[0] 5.105 2.936
CoreSF2Config_0.MDDR_PENABLE M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q CoreSF2Config_0_MDDR_APBmslave_PENABLE 0.108 3.101
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[5] CoreSF2Config_0_MDDR_APBmslave_PRDATA[5] 5.289 3.103
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[14] CoreSF2Config_0_MDDR_APBmslave_PRDATA[14] 5.262 3.130
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[2] CoreSF2Config_0_MDDR_APBmslave_PRDATA[2] 5.251 3.141
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[10] CoreSF2Config_0_MDDR_APBmslave_PRDATA[10] 5.188 3.204
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PRDATA[11] CoreSF2Config_0_MDDR_APBmslave_PRDATA[11] 5.176 3.216
=======================================================================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
M2S_SOM_MSS_0.MSS_ADLIB_INST M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_050 MDDR_FABRIC_PSEL CoreSF2Config_0_MDDR_APBmslave_PSELx 4.285 1.788
CoreSF2Config_0.FIC_2_APB_M_PRDATA[0] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 4.745 1.942
CoreSF2Config_0.FIC_2_APB_M_PRDATA[1] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[1] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[2] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[3] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[4] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[5] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[6] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[7] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[7] 4.745 1.987
CoreSF2Config_0.FIC_2_APB_M_PRDATA[8] M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[8] 4.745 1.987
======================================================================================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 5.000
- Setup time: 0.715
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 4.285
- Propagation time: 2.498
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 1.788
Number of logic level(s): 1
Starting point: CoreSF2Config_0.psel / Q
Ending point: M2S_SOM_MSS_0.MSS_ADLIB_INST / MDDR_FABRIC_PSEL
The start point is clocked by M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK
The end point is clocked by M2S_SOM_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------------
CoreSF2Config_0.psel SLE Q Out 0.108 0.108 -
psel Net - - 0.778 - 4
CoreSF2Config_0.paddr_RNI6MFU[12] CFG4 D In - 0.886 -
CoreSF2Config_0.paddr_RNI6MFU[12] CFG4 Y Out 0.470 1.356 -
CoreSF2Config_0_MDDR_APBmslave_PSELx Net - - 1.142 - 18
M2S_SOM_MSS_0.MSS_ADLIB_INST MSS_050 MDDR_FABRIC_PSEL In - 2.498 -
==================================================================================================================
Total path delay (propagation time + setup) of 3.212 is 1.293(40.2%) logic and 1.920(59.8%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
====================================
Detailed Report for Clock: M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------------------
CoreSF2Reset_0.count[3] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[3] 0.108 7.082
CoreSF2Reset_0.count[7] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[7] 0.108 7.098
CoreSF2Reset_0.count[0] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[0] 0.087 7.104
CoreSF2Reset_0.count[2] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[2] 0.108 7.344
CoreSF2Reset_0.count[6] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[6] 0.108 7.360
CoreSF2Reset_0.count[4] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[4] 0.108 7.383
CoreSF2Reset_0.count[5] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[5] 0.108 7.403
CoreSF2Reset_0.sm0_state[5] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q sm0_state[5] 0.108 7.409
CoreSF2Reset_0.count[1] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[1] 0.108 7.431
CoreSF2Reset_0.count[8] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE Q count[8] 0.108 7.433
===========================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
CoreSF2Reset_0.count[13] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[13] 9.745 7.082
CoreSF2Reset_0.count[12] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[12] 9.745 7.098
CoreSF2Reset_0.count_130us M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE EN count_130us4 9.662 7.104
CoreSF2Reset_0.count_ddr M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE EN count_ddr4 9.662 7.104
CoreSF2Reset_0.count[11] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[11] 9.745 7.114
CoreSF2Reset_0.count[10] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[10] 9.745 7.131
CoreSF2Reset_0.count[9] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[9] 9.745 7.147
CoreSF2Reset_0.count[8] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[8] 9.745 7.386
CoreSF2Reset_0.count[7] M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE D count_s[7] 9.745 7.403
CoreSF2Reset_0.count_enable M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock SLE EN un1_next_init_done_rcosc_0_sqmuxa_0 9.662 7.409
===================================================================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.255
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.745
- Propagation time: 2.663
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 7.082
Number of logic level(s): 7
Starting point: CoreSF2Reset_0.count[3] / Q
Ending point: CoreSF2Reset_0.count[13] / D
The start point is clocked by M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock [rising] on pin CLK
The end point is clocked by M2S_SOM_OSC_0_OSC|RCOSC_25_50MHZ_O2F_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
CoreSF2Reset_0.count[3] SLE Q Out 0.108 0.108 -
count[3] Net - - 0.778 - 4
CoreSF2Reset_0.count_cry_1[12] ARI1 D In - 0.886 -
CoreSF2Reset_0.count_cry_1[12] ARI1 FCO Out 0.505 1.391 -
count_cry_1_FCO[12] Net - - 0.000 - 1
CoreSF2Reset_0.count_cry_3[12] ARI1 FCI In - 1.391 -
CoreSF2Reset_0.count_cry_3[12] ARI1 FCO Out 0.016 1.408 -
count_cry_3_FCO[12] Net - - 0.000 - 1
CoreSF2Reset_0.count_cry[9] ARI1 FCI In - 1.408 -
CoreSF2Reset_0.count_cry[9] ARI1 FCO Out 0.016 1.424 -
count_cry[9] Net - - 0.000 - 1
CoreSF2Reset_0.count_cry[10] ARI1 FCI In - 1.424 -
CoreSF2Reset_0.count_cry[10] ARI1 FCO Out 0.016 1.440 -
count_cry[10] Net - - 0.000 - 1
CoreSF2Reset_0.count_cry[11] ARI1 FCI In - 1.440 -
CoreSF2Reset_0.count_cry[11] ARI1 FCO Out 0.016 1.457 -
count_cry[11] Net - - 0.000 - 1
CoreSF2Reset_0.count_cry[12] ARI1 FCI In - 1.457 -
CoreSF2Reset_0.count_cry[12] ARI1 FCO Out 0.016 1.473 -
count_cry[12] Net - - 0.000 - 1
CoreSF2Reset_0.count_s[13] ARI1 FCI In - 1.473 -
CoreSF2Reset_0.count_s[13] ARI1 S Out 0.073 1.546 -
count_s[13] Net - - 1.117 - 1
CoreSF2Reset_0.count[13] SLE D In - 2.663 -
=============================================================================================
Total path delay (propagation time + setup) of 2.918 is 1.023(35.1%) logic and 1.895(64.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------
OSC_0.I_RCOSC_25_50MHZ System RCOSC_25_50MHZ CLKOUT N_RCOSC_25_50MHZ_CLKOUT 0.000 8.883
OSC_0.I_XTLOSC System XTLOSC CLKOUT OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 0.000 8.883
============================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------------
FCCC_0.CCC_INST System CCC XTLOSC OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 10.000 8.883
OSC_0.I_RCOSC_25_50MHZ_FAB System RCOSC_25_50MHZ_FAB A N_RCOSC_25_50MHZ_CLKOUT 10.000 8.883
=====================================================================================================================================
Worst Path Information
View Worst Path in Analyst
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.000
+ Clock delay at ending point: 0.000 (ideal)
+ Estimated clock delay at ending point: 0.000
= Required time: 10.000
- Propagation time: 1.117
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 8.883
Number of logic level(s): 0
Starting point: OSC_0.I_RCOSC_25_50MHZ / CLKOUT
Ending point: OSC_0.I_RCOSC_25_50MHZ_FAB / A
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
OSC_0.I_RCOSC_25_50MHZ RCOSC_25_50MHZ CLKOUT Out 0.000 0.000 -
N_RCOSC_25_50MHZ_CLKOUT Net - - 1.117 - 1
OSC_0.I_RCOSC_25_50MHZ_FAB RCOSC_25_50MHZ_FAB A In - 1.117 -
=========================================================================================================
Total path delay (propagation time + setup) of 1.117 is 0.000(0.0%) logic and 1.117(100.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for M2S_SOM
Mapping to part: m2s050tfbga484std
Cell usage:
CCC 1 use
CLKINT 5 uses
MSS_050 1 use
RCOSC_25_50MHZ 1 use
RCOSC_25_50MHZ_FAB 1 use
SYSRESET 1 use
XTLOSC 1 use
CFG1 3 uses
CFG2 27 uses
CFG3 12 uses
CFG4 19 uses
Carry primitives used for arithmetic functions:
ARI1 16 uses
Sequential Cells:
SLE 93 uses
Registers not packed on I/O Pads: 93
DSP Blocks: 0
I/O ports: 90
I/O primitives: 87
BIBUF 29 uses
INBUF 16 uses
OUTBUF 37 uses
OUTBUF_DIFF 1 use
TRIBUFF 4 uses
Global Clock Buffers: 5
Total LUTs: 61
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 33MB peak: 79MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jun 25 17:08:02 2013
###########################################################]
Premap Report