#Build: Synplify Pro F-2012.03M-SP2-SF2 , Build 129R, Aug 12 2012 #install: C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2 #OS: Windows XP 5.1 #Hostname: ANDREY2 #Implementation: synthesis $ Start of Compile #Mon Feb 04 16:14:03 2013 Synopsys Verilog Compiler, version comp201203rcp1, Build 129R, built Aug 12 2012 @N: : | Running in 32-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\scemi_pipes.svh" @I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\hypermods.v" @I::"C:\Actelprj\M2S-SOM-2A\component\Actel\SgCore\CCC\2.0.005\ccc_comps.v" @I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\CCC_0\g4m_system_CCC_0_CCC.v" @I::"C:\Actelprj\M2S-SOM-2A\component\Actel\DirectCore\CoreSF2Config\0.1.6\rtl\vlog\core\coresf2config.v" @I::"C:\Actelprj\M2S-SOM-2A\component\Actel\DirectCore\CoreSF2Reset\0.1.6\rtl\vlog\core\coresf2reset.v" @I::"C:\Actelprj\M2S-SOM-2A\component\Actel\SgCore\OSC\0.0.502\osc_comps.v" @I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\FABOSC_0\g4m_system_FABOSC_0_OSC.v" @I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_MSS\g4m_system_MSS_tmp_syn.v" @I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_MSS\g4m_system_MSS.v" @I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\g4m_system.v" @I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_top\g4m_system_top.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module g4m_system_top @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF @N:CG364 : smartfusion2.v(371) | Synthesizing module VCC @N:CG364 : smartfusion2.v(367) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : ccc_comps.v(2) | Synthesizing module CCC @N:CG364 : g4m_system_CCC_0_CCC.v(5) | Synthesizing module g4m_system_CCC_0_CCC @N:CG364 : coresf2config.v(21) | Synthesizing module CoreSF2Config @N:CG364 : coresf2reset.v(22) | Synthesizing module CoreSF2Reset FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000011 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 COUNT_130us=32'b00000000000000000001100101100100 COUNT_DDR=32'b00000000000000000010011100010000 COUNT_MAX=32'b00000000000000000010011100010000 COUNT_WIDTH=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreSF2Reset_Z1 @N:CL177 : coresf2reset.v(402) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coresf2reset.v(402) | Sharing sequential element fpll_lock_q1. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : osc_comps.v(23) | Synthesizing module XTLOSC @N:CG364 : g4m_system_FABOSC_0_OSC.v(5) | Synthesizing module g4m_system_FABOSC_0_OSC @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : g4m_system_MSS_tmp_syn.v(5) | Synthesizing module MSS_050 @N:CG364 : g4m_system_MSS.v(9) | Synthesizing module g4m_system_MSS @N:CG364 : smartfusion2.v(741) | Synthesizing module SYSRESET @N:CG364 : g4m_system.v(9) | Synthesizing module g4m_system @N:CG364 : g4m_system_top.v(9) | Synthesizing module g4m_system_top @W:CL157 : g4m_system_FABOSC_0_OSC.v(18) | *Output RCOSC_25_50MHZ_MSS has undriven bits -- simulation mismatch possible. @W:CL157 : g4m_system_FABOSC_0_OSC.v(19) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : g4m_system_FABOSC_0_OSC.v(21) | *Output RCOSC_1MHZ_MSS has undriven bits -- simulation mismatch possible. @W:CL157 : g4m_system_FABOSC_0_OSC.v(22) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : g4m_system_FABOSC_0_OSC.v(23) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : g4m_system_FABOSC_0_OSC.v(24) | *Output XTLOSC_MSS has undriven bits -- simulation mismatch possible. @W:CL157 : g4m_system_FABOSC_0_OSC.v(26) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @N:CL177 : coresf2reset.v(402) | Sharing sequential element fpll_lock_q2. @N:CL177 : coresf2reset.v(402) | Sharing sequential element sdif0_spll_lock_q2. @N:CL201 : coresf2reset.v(656) | Trying to extract state machine for register sm2_state Extracted state machine for register sm2_state State machine has 2 reachable states with original encodings of: 000 001 @N:CL201 : coresf2reset.v(608) | Trying to extract state machine for register sm1_state Extracted state machine for register sm1_state State machine has 2 reachable states with original encodings of: 000 001 @N:CL201 : coresf2reset.v(517) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coresf2reset.v(49) | Input FPLL_LOCK is unused @W:CL159 : coresf2reset.v(52) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coresf2reset.v(56) | Input SDIF1_SPLL_LOCK is unused @N:CL201 : coresf2config.v(293) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 04 16:14:03 2013 ###########################################################]