#Build: Synplify Pro F-2012.03M-SP2-SF2 , Build 129R, Aug 12 2012
#install: C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2
#OS: Windows XP 5.1
#Hostname: ANDREY2

$ Start of Compile
#Mon Feb 04 16:13:48 2013

Synopsys Verilog Compiler, version comp201203rcp1, Build 129R, built Aug 12 2012
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\generic\smartfusion2.v"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\umr_capim.v"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\scemi_objects.v"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\scemi_pipes.svh"
@I::"C:\Microsemi\Libero_v11.0_Beta\Synopsys\synplify_F201203MSP2SF2\lib\vlog\hypermods.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\SgCore\CCC\2.0.005\ccc_comps.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\CCC_0\g4m_system_CCC_0_CCC.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\DirectCore\CoreSF2Config\0.1.6\rtl\vlog\core\coresf2config.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\DirectCore\CoreSF2Reset\0.1.6\rtl\vlog\core\coresf2reset.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\Actel\SgCore\OSC\0.0.502\osc_comps.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\FABOSC_0\g4m_system_FABOSC_0_OSC.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_MSS\g4m_system_MSS_tmp_syn.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_MSS\g4m_system_MSS.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system\g4m_system.v"
@I::"C:\Actelprj\M2S-SOM-2A\component\work\g4m_system_top\g4m_system_top.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module g4m_system_top
@N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF

@N:CG364 : smartfusion2.v(371) | Synthesizing module VCC

@N:CG364 : smartfusion2.v(367) | Synthesizing module GND

@N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

@N:CG364 : ccc_comps.v(2) | Synthesizing module CCC

@N:CG364 : g4m_system_CCC_0_CCC.v(5) | Synthesizing module g4m_system_CCC_0_CCC

@N:CG364 : coresf2config.v(21) | Synthesizing module CoreSF2Config

@N:CG364 : coresf2reset.v(22) | Synthesizing module CoreSF2Reset

	FAMILY=32'b00000000000000000000000000010011
	EXT_RESET_CFG=32'b00000000000000000000000000000011
	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
	MDDR_IN_USE=32'b00000000000000000000000000000001
	FDDR_IN_USE=32'b00000000000000000000000000000000
	SDIF0_IN_USE=32'b00000000000000000000000000000000
	SDIF1_IN_USE=32'b00000000000000000000000000000000
	DDR_WAIT=32'b00000000000000000000000011001000
	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
	COUNT_130us=32'b00000000000000000001100101100100
	COUNT_DDR=32'b00000000000000000010011100010000
	COUNT_MAX=32'b00000000000000000010011100010000
	COUNT_WIDTH=32'b00000000000000000000000000001110
	S0=32'b00000000000000000000000000000000
	S1=32'b00000000000000000000000000000001
	S2=32'b00000000000000000000000000000010
	S3=32'b00000000000000000000000000000011
	S4=32'b00000000000000000000000000000100
	S5=32'b00000000000000000000000000000101
	S6=32'b00000000000000000000000000000110
   Generated name = CoreSF2Reset_Z1

@N:CL177 : coresf2reset.v(402) | Sharing sequential element sdif0_spll_lock_q1.
@N:CL177 : coresf2reset.v(402) | Sharing sequential element fpll_lock_q1.
@N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

@N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

@N:CG364 : osc_comps.v(23) | Synthesizing module XTLOSC

@N:CG364 : g4m_system_FABOSC_0_OSC.v(5) | Synthesizing module g4m_system_FABOSC_0_OSC

@N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF

@N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF

@N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

@N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

@N:CG364 : g4m_system_MSS_tmp_syn.v(5) | Synthesizing module MSS_050

@N:CG364 : g4m_system_MSS.v(9) | Synthesizing module g4m_system_MSS

@N:CG364 : smartfusion2.v(741) | Synthesizing module SYSRESET

@N:CG364 : g4m_system.v(9) | Synthesizing module g4m_system

@N:CG364 : g4m_system_top.v(9) | Synthesizing module g4m_system_top

@W:CL157 : g4m_system_FABOSC_0_OSC.v(18) | *Output RCOSC_25_50MHZ_MSS has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(19) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(21) | *Output RCOSC_1MHZ_MSS has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(22) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(23) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(24) | *Output XTLOSC_MSS has undriven bits -- simulation mismatch possible.
@W:CL157 : g4m_system_FABOSC_0_OSC.v(26) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@N:CL177 : coresf2reset.v(402) | Sharing sequential element fpll_lock_q2.
@N:CL177 : coresf2reset.v(402) | Sharing sequential element sdif0_spll_lock_q2.
@N:CL201 : coresf2reset.v(656) | Trying to extract state machine for register sm2_state
Extracted state machine for register sm2_state
State machine has 2 reachable states with original encodings of:
   000
   001
@N:CL201 : coresf2reset.v(608) | Trying to extract state machine for register sm1_state
Extracted state machine for register sm1_state
State machine has 2 reachable states with original encodings of:
   000
   001
@N:CL201 : coresf2reset.v(517) | Trying to extract state machine for register sm0_state
Extracted state machine for register sm0_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : coresf2reset.v(49) | Input FPLL_LOCK is unused
@W:CL159 : coresf2reset.v(52) | Input SDIF0_SPLL_LOCK is unused
@W:CL159 : coresf2reset.v(56) | Input SDIF1_SPLL_LOCK is unused
@N:CL201 : coresf2config.v(293) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Feb 04 16:13:49 2013

###########################################################]
Premap Report

Synopsys Generic Technology Pre-mapping, Version mapact, Build 768R, Built Aug 13 2012 09:36:57
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP2-SF2 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Reading constraint file: C:\Actelprj\M2S-SOM-2A\constraint\g4m_system_top_synthesis.sdc
Linked File: g4m_system_top_scck.rpt
Printing clock  summary report in "C:\Actelprj\M2S-SOM-2A\synthesis\g4m_system_top_scck.rpt" file 
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  
@N:MF547 :  | Generated clock conversion disabled  

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)


Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)


Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)

@W:BN132 : coresf2reset.v(517) | Removing sequential instance SDIF1_CORE_RESET_N,  because it is equivalent to instance SDIF0_CORE_RESET_N
@W:BN132 : coresf2reset.v(608) | Removing sequential instance MSS_RESET_N_F2M,  because it is equivalent to instance M3_RESET_N
@W:BN132 : coresf2reset.v(517) | Removing sequential instance SDIF1_PHY_RESET_N,  because it is equivalent to instance SDIF0_PHY_RESET_N
@W:BN132 : coresf2reset.v(517) | Removing sequential instance MDDR_DDR_AXI_S_CORE_RESET_N,  because it is equivalent to instance FDDR_CORE_RESET_N


Clock Summary
**************

Start                               Requested     Requested     Clock        Clock              
Clock                               Frequency     Period        Type         Group              
------------------------------------------------------------------------------------------------
System                              1.0 MHz       1000.000      system       system_clkgroup    
GL0_net_inferred_clock              83.0 MHz      12.048        declared     Inferred_clkgroup_0
50_MHz_RC_Clock                     50.0 MHz      20.000        declared     Inferred_clkgroup_1
FIC_2_APB_M_PCLK_inferred_clock     41.5 MHz      24.096        declared     Inferred_clkgroup_2
MAC_MII_RX_CLK                      25.0 MHz      40.000        declared     MAC_Clocks         
MAC_MII_TX_CLK                      25.0 MHz      40.000        declared     MAC_Clocks         
================================================================================================

syn_allowed_resources : blockrams=69  set on top level netlist g4m_system_top

Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 72MB)

@N:BN225 :  | Writing default property annotation file C:\Actelprj\M2S-SOM-2A\synthesis\g4m_system_top.sap. 
Pre-mapping successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 37MB peak: 72MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Feb 04 16:13:49 2013

###########################################################]
Synopsys Generic Technology Mapper, Version mapact, Build 768R, Built Aug 13 2012 09:36:57
Copyright (C) 1994-2012, Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version F-2012.03M-SP2-SF2 

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Reading constraint file: C:\Actelprj\M2S-SOM-2A\constraint\g4m_system_top_synthesis.sdc
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  
@N:MF547 :  | Generated clock conversion disabled  

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)


Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)


Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 54MB)



Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 72MB)

@W:MO111 : g4m_system_fabosc_0_osc.v(26) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:MO111 : g4m_system_fabosc_0_osc.v(24) | Tristate driver XTLOSC_MSS on net XTLOSC_MSS has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:MO111 : g4m_system_fabosc_0_osc.v(18) | Tristate driver RCOSC_25_50MHZ_MSS on net RCOSC_25_50MHZ_MSS has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:MO111 : g4m_system_fabosc_0_osc.v(19) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:MO111 : g4m_system_fabosc_0_osc.v(23) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:MO111 : g4m_system_fabosc_0_osc.v(21) | Tristate driver RCOSC_1MHZ_MSS on net RCOSC_1MHZ_MSS has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:MO111 : g4m_system_fabosc_0_osc.v(22) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module g4m_system_FABOSC_0_OSC) 
@W:BN132 : coresf2reset.v(517) | Removing sequential instance SDIF1_CORE_RESET_N,  because it is equivalent to instance SDIF0_CORE_RESET_N
@W:BN132 : coresf2reset.v(608) | Removing sequential instance MSS_RESET_N_F2M,  because it is equivalent to instance M3_RESET_N
@W:BN132 : coresf2reset.v(517) | Removing sequential instance SDIF1_PHY_RESET_N,  because it is equivalent to instance SDIF0_PHY_RESET_N
@W:BN132 : coresf2reset.v(517) | Removing sequential instance MDDR_DDR_AXI_S_CORE_RESET_N,  because it is equivalent to instance FDDR_CORE_RESET_N
@W:MO171 : coresf2reset.v(317) | Sequential instance CORESF2RESET_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W:BN132 : coresf2reset.v(331) | Removing sequential instance g4m_system_0.CORESF2RESET_0.sm2_areset_n_q1,  because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm0_areset_n_q1
@W:BN132 : coresf2reset.v(331) | Removing sequential instance g4m_system_0.CORESF2RESET_0.sm2_areset_n_rcosc,  because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm0_areset_n_rcosc

Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

Encoding state machine state[2:0] (netlist:statemachine)
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[31],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[30]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[30],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[29]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[29],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[28]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[28],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[27]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[27],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[26]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[26],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[25]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[25],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[24]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[24],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[23]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[23],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[22]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[22],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[21]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[21],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[20]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[20],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[19]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[19],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[18]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[18],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[17]
@W:BN132 : coresf2config.v(370) | Removing instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[17],  because it is equivalent to instance g4m_system_0.CORESF2CONFIG_0.FIC_2_APB_M_PRDATA[16]
@N:BN362 : coresf2config.v(370) | Removing sequential instance FIC_2_APB_M_PRDATA[16] in hierarchy view:work.CoreSF2Config(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(370) | Boundary register FIC_2_APB_M_PRDATA[16] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
Encoding state machine sm0_state[6:0] (netlist:statemachine)
original code -> new code
   000 -> 0000001
   001 -> 0000010
   010 -> 0000100
   011 -> 0001000
   100 -> 0010000
   101 -> 0100000
   110 -> 1000000
Encoding state machine sm2_state[1:0] (netlist:statemachine)
original code -> new code
   000 -> 0
   001 -> 1
Encoding state machine sm1_state[1:0] (netlist:statemachine)
original code -> new code
   000 -> 0
   001 -> 1
@W:MO129 : coresf2reset.v(608) | Sequential instance g4m_system_0.CORESF2RESET_0.sm1_state[0] reduced to a combinational gate by constant propagation
@N: : coresf2reset.v(674) | Found counter in view:work.CoreSF2Reset_Z1(verilog) inst count[13:0]
@W:BN132 : coresf2reset.v(402) | Removing sequential instance g4m_system_0.CORESF2RESET_0.sdif1_spll_lock_q1,  because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm2_state[0]
@N:BN362 : coresf2reset.v(608) | Removing sequential instance M3_RESET_N in hierarchy view:work.CoreSF2Reset_Z1(verilog) because there are no references to its outputs 
@W:BN132 : coresf2reset.v(517) | Removing instance g4m_system_0.CORESF2RESET_0.USER_FAB_RESET_N,  because it is equivalent to instance g4m_system_0.CORESF2RESET_0.sm0_state[6]
@N:BN362 : coresf2reset.v(517) | Removing sequential instance g4m_system_0.CORESF2RESET_0.FDDR_CORE_RESET_N in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@N:BN362 : coresf2reset.v(517) | Removing sequential instance g4m_system_0.CORESF2RESET_0.SDIF0_CORE_RESET_N in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@N:BN362 : coresf2reset.v(517) | Removing sequential instance g4m_system_0.CORESF2RESET_0.SDIF0_PHY_RESET_N in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[14] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[14] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[11] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PADDR_1[11] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[31] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[31] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[30] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[30] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[29] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[29] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[28] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[28] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[27] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[27] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[26] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[26] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[25] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[25] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[24] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[24] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[23] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[23] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[22] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[22] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[21] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[21] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[20] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[20] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[19] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[19] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[18] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[18] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[17] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[17] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 
@N:BN362 : coresf2config.v(131) | Removing sequential instance g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[16] in hierarchy view:work.g4m_system_top(verilog) because there are no references to its outputs 
@A:BN291 : coresf2config.v(131) | Boundary register g4m_system_0.CORESF2CONFIG_0.SDIF1_PWDATA_1[16] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. 

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

Constraint Checker successful!

At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 73MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Feb 04 16:13:50 2013

###########################################################]