#Build: Synplify Pro 8.8, Build 008R, Dec  7 2006
#install: D:\Program Files\Synplicity\fpga_88
#OS: Windows XP 5.1
#Hostname: WXPL-MCCARTHYT1

#Implementation: synthesis

#Thu Mar 01 15:18:32 2007

$ Start of Compile
#Thu Mar 01 15:18:32 2007

Synplicity Verilog Compiler, version 3.7.5, Build 103R, built Jan 30 2007
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Program Files\Synplicity\fpga_88\lib\proasic\fusion.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\PLL_40_10\PLL_40_10.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\NGM\NGM.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog_assc_ram.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\assc.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog_assc_wrapper.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog_smev_ram.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\smev.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog_smev_wrapper.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog_smtr_ram.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\smtr.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog_smtr_wrapper.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\Analog\Analog.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg_xa.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg_xb.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg_xc.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg_xd.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg_xe.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg_xf.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\common\verilog\initcfg.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\NVM_sys\NVM_sys_init_wrapper.v"
@I::"D:\Actelprj\VT_Mon_vlog\smartgen\NVM_sys\NVM_sys.v"
@I::"D:\Actelprj\VT_Mon_vlog\hdl\VT_Mon.v"
Verilog syntax check successful!
File D:\Actelprj\VT_Mon_vlog\hdl\VT_Mon.v changed - recompiling
Selecting top level module VT_Mon
@N:CG364 : fusion.v(2043) | Synthesizing module VCC

@N:CG364 : fusion.v(1224) | Synthesizing module GND

@N:CG364 : fusion.v(2974) | Synthesizing module PLL

@N:CG364 : PLL_40_10.v(5) | Synthesizing module PLL_40_10

@N:CG364 : fusion.v(3380) | Synthesizing module NGMUX

@N:CG364 : NGM.v(5) | Synthesizing module NGM

@W:CL168 : NGM.v(11) | Pruning instance GND_1_net - not in use ...

@N:CG364 : fusion.v(3203) | Synthesizing module AB

@N:CG364 : fusion.v(3370) | Synthesizing module INBUF_A

@N:CG364 : fusion.v(2267) | Synthesizing module RAM4K9

@N:CG364 : Analog_smtr_ram.v(5) | Synthesizing module Analog_smtr_ram

@N:CG364 : fusion.v(1561) | Synthesizing module OR2

@N:CG364 : fusion.v(3375) | Synthesizing module OUTBUF_A

@N:CG364 : smtr.v(10) | Synthesizing module ccfdxrhchsz

	qjnhkksszkf=32'b00000000000000000000000000000000
	hbgvpqcgtwm=32'b00000000000000000000000000000000
	fnscgtbnskd=32'b00000000000000000000000000000000
	xkcbxcnxxhg=32'b00000000000000000000000000001001
	cvczfvkpmqh=32'b00000000000000000000000000001001
	dgswbvgbtfw=32'b00000000000000000000000000000000
	twqmbkvsqjv=4'b0010
	ffskdxgczkf=4'b0011
	jwgwqvwgzqc=4'b0100
	hdmrhsdqkpf=4'b0101
	vfhwbpmxnhg=4'b0110
	hjsptcsxwwj=4'b0111
	qkfdnddgfnr=4'b1000
	hvdtwfkzgjf=4'b1001
	tgmgxbkhgvv=4'b1010
	mrkkbfgjnsm=4'b1011
	fqsggvsnbpw=4'b1100
	vkzrtdvqxtm=4'b1101
	cprxxpgqtzv=4'b1110
	bzfzwfqrsfh=4'b1111
	gwcnpmdcdgf=2'b00
	cxqfrrsmjms=2'b01
	scfrdfnbqsw=2'b10
	tddtwhmsmxw=4'b0000
	csrjrbfvktn=4'b0001
	vrqwnsvfhbf=4'b0010
	tcngxxfgmdg=4'b0011
	vwzxznxmxjj=4'b0100
	bfsztxmjbwz=4'b0101
	ncvfznsdsmv=4'b0110
	nksjwxsrvfg=4'b0111
	jhdgkzrksxb=4'b1000
	mxpxttqxdhv=4'b1001
	whzkgttntpq=4'b1010
	pgtwqqmcgdx=4'b1011
	nhjqdsptgfp=9'b111111111
	gwmqzbkfvkx=7'b0000000
   Generated name = ccfdxrhchsz_Z1
@W:CG360 : smtr.v(58) | No assignment to wire jjnnjkrjzfq

@W:CG360 : smtr.v(60) | No assignment to wire mgqspspvvwp

@W:CG360 : smtr.v(65) | No assignment to wire czjszchcxth

@W:CG360 : smtr.v(67) | No assignment to wire rdqhbcjchvq

@W:CL169 : smtr.v(91) | Pruning Register bpkzfmkvkrj[1:0] 

@W:CL169 : smtr.v(91) | Pruning Register bvjxfbhxgkj[4:0] 

@N:CG364 : smtr.v(267) | Synthesizing module SMTR

	GPI_BITS=32'b00000000000000000000000000000000
	GPO_BITS=32'b00000000000000000000000000000000
	ALLOW_USER_TR=32'b00000000000000000000000000000000
	EV_ASIZE=32'b00000000000000000000000000001001
	TR_ASIZE=32'b00000000000000000000000000001001
	USE_NON_G3=32'b00000000000000000000000000000000
   Generated name = SMTR_0s_0s_0s_9s_9s_0s
@N:CG364 : Analog_smtr_wrapper.v(1) | Synthesizing module Analog_smtr_wrapper

@N:CG364 : Analog_assc_ram.v(5) | Synthesizing module Analog_assc_ram

@N:CG364 : smev.v(10) | Synthesizing module nbnjbfrkqwq

	xpcbfxxdxkn=32'b00000000000000000000000000000110
	nktdnxxpfkw=32'b00000000000000000000000000000000
	ggtrvzfhvzg=32'b00000000000000000000000000000001
	wqxrhkntcsq=32'b00000000000000000000000000000000
	fnkkfbknbsc=32'b00000000000000000000000000000000
	cvjhxdkdhtp=32'b00000000000000000000000000000001
	tbfvnhctzpk=32'b00000000000000000000000000001001
	gzpxmwsppbw=32'b00000000000000000000000000000101
	gqvfcjcxrbx=32'b00000000000000000000000000000000
	bbgbwbsfrfg=3'b000
	xbpzprjgbtz=3'b001
	gwnrsjgrpbc=3'b010
	jswmkwkntrs=3'b011
	cgrzbdcbzpz=3'b100
	zddwkjwwzbw=3'b101
	nrpbqkqfsmf=3'b110
	jgnwnzmddbg=3'b111
	nmwcwxjntmm=2'b00
	pcfxjtkxtsg=2'b01
	xwwgksgtkqh=3'b011
	njddmfhbdwc=3'b100
	kntgqgfbzkr=5'b00000
	cgxqzmxpnxk=5'b00001
	zjkzxqtrnnb=5'b00010
	qrqqppcxnvn=5'b00011
	fvkvddpjhhn=5'b00100
	ggzhpgqrzwh=5'b00101
	xxntrgztxmd=5'b00110
	fjkwxwrhjth=5'b00111
	fwhsjhtxbzz=5'b01000
	gxvwpbbfszd=5'b01001
	sdcwbhhndvx=5'b01010
	rqsqdpqbsvd=5'b01011
	hqxrmvjrpxb=5'b01100
	tkfbpdjdwdh=5'b01101
	znqvsmrcdpb=5'b01110
	szzwndnzvgm=5'b01111
	qrtrwbcbrcg=5'b10000
	fkfmkfrjbkn=5'b10001
	pnwpqmrtsvr=9'b111111111
	zzrrppgmfrr=6'b000000
	cmxrrdpdrcs=8'b00000000
	shsxpvrhshq=9'b000000000
   Generated name = nbnjbfrkqwq_Z2
@W:CG133 : smev.v(62) | No assignment to smsgrfvbrts
@N:CG364 : smev.v(289) | Synthesizing module SMEV

	TS_WIDTH=32'b00000000000000000000000000000110
	ALLOW_USER_EV=32'b00000000000000000000000000000000
	ALLOW_DLPF=32'b00000000000000000000000000000001
	ALLOW_A_PLUS_B=32'b00000000000000000000000000000000
	ALLOW_A_MINUS_B=32'b00000000000000000000000000000000
	ALLOW_A_GT_B=32'b00000000000000000000000000000001
	EV_ASIZE=32'b00000000000000000000000000001001
	ST_CNT_WIDTH=32'b00000000000000000000000000000101
	USE_NON_G3=32'b00000000000000000000000000000000
   Generated name = SMEV_6s_0s_1s_0s_0s_1s_9s_5s_0s
@N:CG364 : Analog_smev_wrapper.v(1) | Synthesizing module Analog_smev_wrapper

@N:CG364 : Analog_smev_ram.v(5) | Synthesizing module Analog_smev_ram

@N:CG364 : assc.v(10) | Synthesizing module fmvgpwbdcxs

	knrjvwspqzm=3'b110
	ddqwgtngbxc=6'b000000
	whxdkdmhjwj=4'b1000
	cpcqjrjtppx=1'b0
	pqqkvvvcbmx=1'b0
	mqbcdwzwhzc=1'b0
	pxzwzhfwkqm=4'b0000
	dgsjdxsjscf=1'b0
	rcbvmqmwnjn=1'b0
	vhxpkfzhvxk=8'b00000000
	kksfgnxtcxn=1'b0
	dggdcrrffcs=8'b00000000
	jphnsqvgftr=10'b0000000000
	csnxdprbsgk=11'b00000000001
	hnvgngcgxqv=3'b000
	nqsmzqnjmrw=3'b001
	zzkwmmdbxsp=3'b010
	rrkzczwdwsc=3'b011
	hjsnsxjgcdh=3'b100
	vxcfjzvsvhk=3'b101
	tmqfdmdqjts=3'b110
	rdqqcddkdwq=3'b111
	bjsvghjhbmx=3'b001
	chgvmjshrrw=3'b010
	bmhfcgnbbxr=3'b011
	gdgczndxskv=3'b100
	kzqsqsbqhrw=3'b101
	wnxmqrmxxnh=3'b110
	hbsskxtsqbt=6'b000000
	tpbpbbzppsz=8'b11111111
	mdqdmchqsjk=4'b0000
	zjjmzcsxggj=4'b0001
	nvnpbtnnhwb=4'b0010
	zgqrpqvjtwm=4'b0011
	rvsskdxmcct=4'b0100
	ptgdvkqmfxz=4'b0101
	rcgmzbqbdhp=4'b0110
	xdbhgfkhtkv=4'b0111
	bjrtpbmfdvt=4'b1000
	jvfmnrmnrsc=4'b1001
	gmccksdwzbb=4'b1010
	pdtbxbcjmqv=4'b1011
	frtsmvmjzjs=4'b1100
	dnkbdnxmrsb=4'b1101
	dtdsjrnddkb=4'b1110
	jqktphcjtcx=4'b1111
   Generated name = fmvgpwbdcxs_Z3
@W:CL169 : assc.v(250) | Pruning Register sxqvnxkkjsh[9:0] 

@W:CL169 : assc.v(250) | Pruning Register kzdxfwqwvrt 

@W:CL169 : assc.v(250) | Pruning Register jzwhhbvmkpk 

@W:CL169 : assc.v(250) | Pruning Register njsdcspkqtt 

@W:CL170 : assc.v(266) | Pruning bit <10> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <9> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <8> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <7> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <6> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <5> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <4> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <3> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <2> of bwngcbddzsh_19[10:0] - not in use ...

@W:CL170 : assc.v(266) | Pruning bit <1> of bwngcbddzsh_19[10:0] - not in use ...

@N:CG364 : assc.v(333) | Synthesizing module ASSC

	TS_WIDTH=3'b110
	TS_RST_VALUE=6'b000000
	DLYCNT_WIDTH=4'b1000
	ALLOW_USER_ASSC=1'b0
	ALLOW_RPT=1'b0
	FIXED_MODE=1'b0
	FIXED_MODE_CONST=4'b0000
	FIXED_VREFSEL_CONST=1'b0
	FIXED_STC=1'b0
	FIXED_STC_CONST=8'b00000000
	FIXED_TVC=1'b0
	FIXED_TVC_CONST=8'b00000000
	ALLOW_CM_STB_BITS=10'b0000000000
	ALLOW_TM_STB_BITS=11'b00000000001
   Generated name = ASSC_Z4
@N:CG364 : Analog_assc_wrapper.v(1) | Synthesizing module Analog_assc_wrapper

@N:CG364 : Analog.v(5) | Synthesizing module Analog

@N:CG364 : fusion.v(3147) | Synthesizing module NVM

@N:CG364 : initcfg_xa.v(10) | Synthesizing module stnpfdkggvx

	znbxfhhzvcr=32'b00000000000000000000000000000100
	cdczdbxmjcn=32'b00000000000000000000000000000010
	tvzdqnwfvfh=3'b000
	zmvpjkpbpxm=3'b001
	xbwfvwmkpbv=3'b010
	qgtqskssqxc=3'b011
	ktpjzjzrqtg=3'b100
	nnkzhsghqkw=3'b101
	mdzgdrhtwkc=3'b110
	tdkqfrncvhq=3'b111
   Generated name = stnpfdkggvx_4s_2s_0_1_2_3_4_5_6_7
@N:CG364 : initcfg_xa.v(51) | Synthesizing module INITCFG_XA

	MAX_CLIENT=32'b00000000000000000000000000000100
	MAX_CLIENT_BITS=32'b00000000000000000000000000000010
   Generated name = INITCFG_XA_4s_2s
@N:CG364 : initcfg_xb.v(10) | Synthesizing module wbsfnwwctpn

	tmxcpsvwjwc=32'b00000000000000000000000000000100
	rchvpvgtdzp=32'b00000000000000000000000000000010
	cqppqjpknwn=4'b0000
	tjjmqmntzrj=4'b0001
	sbbghcmnjcd=4'b0010
	phhmrjsbhxm=4'b0011
	rqxvwvrbcwj=4'b0100
	bfdbzszvjts=4'b0101
	fxnsrcgnnwv=4'b0110
	wjnfncxbjmm=4'b0111
	vqvvxnwqfkz=4'b1000
   Generated name = wbsfnwwctpn_Z5
@N:CG364 : initcfg_xb.v(65) | Synthesizing module INITCFG_XB

	MAX_CLIENT=32'b00000000000000000000000000000100
	MAX_CLIENT_BITS=32'b00000000000000000000000000000010
   Generated name = INITCFG_XB_4s_2s
@N:CG364 : initcfg_xc.v(10) | Synthesizing module ffppvfwnggt

	rptpxqccxqw=32'b00000000000000000000000000000100
	gvwtbkksmbj=32'b00000000000000000000000000000010
	zpzqwtrdvbp=32'b00000000000000000000000000001001
   Generated name = ffppvfwnggt_4s_2s_9s
@N:CG364 : initcfg_xc.v(155) | Synthesizing module INITCFG_XC

	MAX_CLIENT=32'b00000000000000000000000000000100
	MAX_CLIENT_BITS=32'b00000000000000000000000000000010
	MAX_WORD_BIT=32'b00000000000000000000000000001001
   Generated name = INITCFG_XC_4s_2s_9s
@N:CG364 : initcfg_xd.v(10) | Synthesizing module dxwqxgdccxc

	pjbfkczqqqn=32'b00000000000000000000000000001001
   Generated name = dxwqxgdccxc_9s
@N:CG364 : initcfg_xd.v(54) | Synthesizing module INITCFG_XD

	MAX_WORD_BIT=32'b00000000000000000000000000001001
   Generated name = INITCFG_XD_9s
@N:CG364 : initcfg_xe.v(10) | Synthesizing module gpbdjfttbjd

	pwsjbpbwfdp=32'b00000000000000000000000000000100
	rszdtxvjmkk=32'b00000000000000000000000000000010
   Generated name = gpbdjfttbjd_4s_2s
@N:CG364 : initcfg_xe.v(26) | Synthesizing module INITCFG_XE

	MAX_CLIENT=32'b00000000000000000000000000000100
	MAX_CLIENT_BITS=32'b00000000000000000000000000000010
   Generated name = INITCFG_XE_4s_2s
@N:CG364 : initcfg_xf.v(10) | Synthesizing module jhmkpjjmdkx

@N:CG364 : initcfg_xf.v(38) | Synthesizing module INITCFG_XF

@N:CG364 : initcfg.v(10) | Synthesizing module grwzcnqmqzm

	hphqhdwdhmf=32'b00000000000000000000000000001001
	chwbfzxpgsp=32'b00000000000000000000000000000100
	mrffkbssmtq=32'b00000000000000000000000000000010
	qwsfndhqmkm=32'b00000000000000000001000000000000
	mnzfvzggbgp=32'b00000000000000000000000000101001
	dqrxdcfppkj=32'b00000000000000000000000000000000
	sgsprpjjzdc=32'b00000000000000000000000000000001
	rsgtbhgqwcc=32'b00000000000000000000000000000000
	bwstmtzrgsf=32'b00000000000000000010000000000000
	krvfnxvdczw=32'b00000000000000000000001000000000
	srsmtfkmzzq=32'b00000000000000000000000000000000
	dfbxgpzpjqp=32'b00000000000000000000000000000001
	cjjhrtwmvpv=32'b00000000000000000000000000000001
	jhgkdhvwcfb=32'b00000000000000001010000000000000
	htwtmbfrnfz=32'b00000000000000000000000001100100
	kgztbhmkskk=32'b00000000000000000000000000000000
	bzqvhzjcdph=32'b00000000000000000000000000000001
	cnxcpvmknsk=32'b00000000000000000000000000000001
	frfwqrrdddg=32'b00000000000000001100000000000000
	xkvjnpdmkkm=32'b00000000000000000000000001101000
	xnmjhccrpbz=32'b00000000000000000000000000000000
	spbwnqbxkkn=32'b00000000000000000000000000000001
	fsqrqsfbjhm=32'b00000000000000000000000000000001
	tfbkdzcghbt=32'b00000000000000000000000000000000
	zzbncfwtcjb=32'b00000000000000000000000000000000
	dpkfnwtwdjx=32'b00000000000000000000000000000000
	zvxxwrbtgqz=32'b00000000000000000000000000000000
	jfjcmxmmgjr=32'b00000000000000000000000000000000
	vrnqqtvpznx=32'b00000000000000000000000000000000
	czxqdxtxdcd=32'b00000000000000000000000000000000
	gvdxfskncvn=32'b00000000000000000000000000000000
	qmvrkmnxnbr=32'b00000000000000000000000000000000
	mjqhrwtncqv=32'b00000000000000000000000000000000
	vnfbfdkcmct=32'b00000000000000000000000000000000
	vxjhvxtcdqc=32'b00000000000000000000000000000000
	cmdcwdfbsqd=32'b00000000000000000000000000000000
	bnjnjsfcbcw=32'b00000000000000000000000000000000
	xkvntfssjpv=32'b00000000000000000000000000000000
	srpkvvkkrzt=32'b00000000000000000000000000000000
	fgkrxwdxwtc=32'b00000000000000000000000000000000
	xkjrjgwpqdm=32'b00000000000000000000000000000000
	zdqqwkgkhhx=32'b00000000000000000000000000000000
	hzgsvvbxngk=32'b00000000000000000000000000000000
	sthncdwvjtw=32'b00000000000000000000000000000000
	tsqgqxvmnhz=32'b00000000000000000000000000000000
	qnzjbnnwknh=32'b00000000000000000000000000000000
	pmnbjxmfgxd=32'b00000000000000000000000000000000
	nqxzdhmssdr=32'b00000000000000000000000000000000
	bnkjcrhcdfs=32'b00000000000000000000000000000000
	wmmrphpmvnv=32'b00000000000000000000000000000000
	dmxmzjbtdmr=32'b00000000000000000000000000000000
	tkftzwrbhbh=32'b00000000000000000000000000000000
	svvgxqdxdfv=32'b00000000000000000000000000000000
	czrwqbddqjn=32'b00000000000000000000000000000000
	nczxtwvzskw=32'b00000000000000000000000000000000
	vcvqnbfhntg=32'b00000000000000000000000000000000
	zfjxqtzgtfg=32'b00000000000000000000000000000000
	tkvdjvhrvvg=32'b00000000000000000000000000000000
	hprgsrzhrfm=32'b00000000000000000000000000000000
	wvxsdzmgnjr=32'b00000000000000000000000000000000
	vmzrgwpkkqm=32'b00000000000000000000000000000000
	sktdchbdzgd=32'b00000000000000000000000000000000
	tgqmncfnssz=32'b00000000000000000000000000000000
	rwbpgntsknz=32'b00000000000000000000000000000000
	rtnjmbcbzsp=32'b00000000000000000000000000000000
	dxpspzjbxvw=32'b00000000000000000000000000000000
	svwmmdmkcxj=32'b00000000000000000000000000000000
	fqwvkwrjzqp=32'b00000000000000000000000000000000
	hrjrtbfwxrz=32'b00000000000000000000000000000000
	ntxtvbcmgpz=32'b00000000000000000000000000000000
	vbwxjbjvxxn=32'b00000000000000000000000000000000
	rssdfnxtdvc=32'b00000000000000000000000000000000
	qqhddwcfdcz=32'b00000000000000000000000000000000
	msnmxsssvws=32'b00000000000000000000000000000000
	dmvxrrpgczz=32'b00000000000000000000000000000000
	mrrhxvjqgwg=32'b00000000000000000000000000000000
	xnspvwjhsrt=32'b00000000000000000000000000000000
	gsgvwbvcxxh=32'b00000000000000000000000000000000
	smgkxmdgnww=32'b00000000000000000000000000000000
	bwqtbcpddzs=32'b00000000000000000000000000000000
	qmmhqcjngdv=32'b00000000000000000000000000000000
	mmncfgsdhxd=32'b00000000000000000000000000000000
	fxwwxvbngvv=32'b00000000000000000000000000000000
	pxxzhqhrxbb=32'b00000000000000000000000000000000
	dqwtkvpgwnq=32'b00000000000000000000000000000000
	pvhbxphxmvf=32'b00000000000000000000000000000000
	rvkfqjhzvct=32'b00000000000000000000000000000000
	rnpdjmgrnth=32'b00000000000000000000000000000000
	mknhpztjddj=32'b00000000000000000000000000000000
	xqfppbdhtsk=32'b00000000000000000000000000000000
	dszbfpkvfbj=32'b00000000000000000000000000000000
	xhjkjhvvsnq=32'b00000000000000000000000000000000
	rwpszkwsmxz=32'b00000000000000000000000000000000
	wxhvvzpspmh=32'b00000000000000000000000000000000
	kknpckfzwtf=32'b00000000000000000000000000000000
	skfpvdnmxmp=32'b00000000000000000000000000000000
	cbjgqdrxwmp=32'b00000000000000000000000000000000
	hzwkdjjmxfs=32'b00000000000000000000000000000000
	bchrncjjwsv=32'b00000000000000000000000000000000
	bfbnckxtmdb=32'b00000000000000000000000000000000
	jkvwdrbrfts=32'b00000000000000000000000000000000
	bmcbrpctvbr=32'b00000000000000000000000000000000
	zdtxzwtxzvs=32'b00000000000000000000000000000000
	tpmcsxpqzbn=32'b00000000000000000000000000000000
	grvkswpvkwq=32'b00000000000000000000000000000000
	jjscqqxjjvv=32'b00000000000000000000000000000000
	jccckstbdxm=32'b00000000000000000000000000000000
	pxjxdpsnwrw=32'b00000000000000000000000000000000
	mrzvztzvgqn=32'b00000000000000000000000000000000
	wtfkktxvfmx=32'b00000000000000000000000000000000
	nxxhhgrxhqs=32'b00000000000000000000000000000000
	mhkvqwkwqbb=32'b00000000000000000000000000000000
	pmrrqbmrcgp=32'b00000000000000000000000000000000
	fnqrcfmrdzn=32'b00000000000000000000000000000000
	vgvrpwwvdss=32'b00000000000000000000000000000000
	pfsbjdzqfvg=32'b00000000000000000000000000000000
	kspfmtsrdgt=32'b00000000000000000000000000000000
	mtvnfqkxztb=32'b00000000000000000000000000000000
	ktvcqzbfwsd=32'b00000000000000000000000000000000
	bzvfztsfwmw=32'b00000000000000000000000000000000
	qdhpcpjhdtx=32'b00000000000000000000000000000000
	jzswvrrbxmj=32'b00000000000000000000000000000000
	sgrkdxfmpms=32'b00000000000000000000000000000000
	ctjqbtwmmbb=32'b00000000000000000000000000000000
	rzgvvbpxdbj=32'b00000000000000000000000000000000
	szcqjdwxxtb=32'b00000000000000000000000000000000
	prkzsrdjzfw=32'b00000000000000000000000000000000
	cjmsxfcqphp=32'b00000000000000000000000000000000
	cbtwsxgjskh=32'b00000000000000000000000000000000
	rdmjjdgbpqc=32'b00000000000000000000000000000000
	xdzvsmzqdcg=32'b00000000000000000000000000000000
	djqmrdpfnmr=32'b00000000000000000000000000000000
	spdkwdsgmfp=32'b00000000000000000000000000000000
	mkjxqvbtvtn=32'b00000000000000000000000000000000
	kjcscgxkwms=32'b00000000000000000000000000000000
	zvmkwvmrjrn=32'b00000000000000000000000000000000
	zqzcmjszsww=32'b00000000000000000000000000000000
	hgdstcphzmj=32'b00000000000000000000000000000000
	mbgtkvbrhxm=32'b00000000000000000000000000000000
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   Generated name = grwzcnqmqzm_Z6
@N:CG364 : initcfg.v(447) | Synthesizing module INITCFG

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   Generated name = INITCFG_Z7
@N:CG364 : NVM_sys_init_wrapper.v(1) | Synthesizing module NVM_sys_init_wrapper

@N:CG364 : NVM_sys.v(5) | Synthesizing module NVM_sys

@W:CL168 : NVM_sys.v(227) | Pruning instance VCC_power_inst1 - not in use ...

@N:CG364 : VT_Mon.v(4) | Synthesizing module VT_Mon

@N:CL201 : initcfg_xb.v(44) | Trying to extract state machine for register crpwsdfhcqq
Extracted state machine for register crpwsdfhcqq
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
@N:CL201 : initcfg_xa.v(37) | Trying to extract state machine for register mwtvnzdkmwm
Extracted state machine for register mwtvnzdkmwm
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N:CL201 : assc.v(243) | Trying to extract state machine for register jzzdfrmzwdj
Extracted state machine for register jzzdfrmzwdj
State machine has 16 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
   1101
   1110
   1111
@W:CL159 : assc.v(26) | Input vhqjcrxqhqk is unused
@W:CL159 : assc.v(27) | Input vhsprbpmpnr is unused
@N:CL201 : smev.v(223) | Trying to extract state machine for register tkcbxxqbtfx
Extracted state machine for register tkcbxxqbtfx
State machine has 18 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
@W:CL159 : smev.v(22) | Input zxrxtxxbsks is unused
@W:CL159 : smev.v(23) | Input zhkvvfnsbjb is unused
@W:CL159 : smev.v(26) | Input mqmgjkmdztb is unused
@N:CL201 : smtr.v(231) | Trying to extract state machine for register frcskdnwvmx
Extracted state machine for register frcskdnwvmx
State machine has 12 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
@W:CL234 : smtr.v(24) | Input port bits <8 to 1> of qxzrwpjhcww[8:0] are unused

@W:CL159 : smtr.v(22) | Input qbrqxpmkpsw is unused
@W:CL159 : smtr.v(22) | Input nktsnhmjrbx is unused
@W:CL159 : smtr.v(25) | Input dnmrkvrtbjn is unused
@END
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Mar 01 15:18:35 2007

###########################################################]
BMEM_GUARD is ON
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 005R, Built Jan 30 2007 19:51:21
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 


Automatic dissolve during optimization of view:work.Analog_smtr_wrapper(verilog) of user_Analog_smtr_wrapper(SMTR_0s_0s_0s_9s_9s_0s)
Automatic dissolve during optimization of view:work.Analog_smev_wrapper(verilog) of user_Analog_smev_wrapper(SMEV_6s_0s_1s_0s_0s_1s_9s_5s_0s)
Automatic dissolve during optimization of view:work.Analog_assc_wrapper(verilog) of user_Analog_assc_wrapper(ASSC_Z4)
Automatic dissolve during optimization of view:work.Analog(verilog) of Analog_assc_wrapper_inst(Analog_assc_wrapper)
Automatic dissolve during optimization of view:work.Analog(verilog) of Analog_smev_ram_inst(Analog_smev_ram)
Automatic dissolve during optimization of view:work.Analog(verilog) of Analog_smev_wrapper_inst(Analog_smev_wrapper)
Automatic dissolve during optimization of view:work.Analog(verilog) of Analog_assc_ram_inst(Analog_assc_ram)
Automatic dissolve during optimization of view:work.Analog(verilog) of Analog_smtr_wrapper_inst(Analog_smtr_wrapper)
Automatic dissolve during optimization of view:work.Analog(verilog) of Analog_smtr_ram_inst(Analog_smtr_ram)
Automatic dissolve during optimization of view:work.grwzcnqmqzm_Z6(verilog) of user_clk_sel(INITCFG_XF)
Automatic dissolve during optimization of view:work.grwzcnqmqzm_Z6(verilog) of valid_client(INITCFG_XE_4s_2s)
Automatic dissolve during optimization of view:work.grwzcnqmqzm_Z6(verilog) of address_gen(INITCFG_XD_9s)
Automatic dissolve during optimization of view:work.grwzcnqmqzm_Z6(verilog) of user_control(INITCFG_XC_4s_2s_9s)
Automatic dissolve during optimization of view:work.grwzcnqmqzm_Z6(verilog) of save_fsm(INITCFG_XB_4s_2s)
Automatic dissolve during optimization of view:work.grwzcnqmqzm_Z6(verilog) of init_fsm(INITCFG_XA_4s_2s)
Automatic dissolve during optimization of view:work.NVM_sys_init_wrapper(verilog) of user_NVM_sys_init_wrapper(INITCFG_Z7)
Automatic dissolve during optimization of view:work.NVM_sys(verilog) of NVM_sys_init_wrapper_inst(NVM_sys_init_wrapper)
Automatic dissolve during optimization of view:work.VT_Mon(verilog) of NGMUX_inst(NGM)
Automatic dissolve during optimization of view:work.VT_Mon(verilog) of PLL_inst(PLL_40_10)
Automatic dissolve at startup in view:work.grwzcnqmqzm_Z6(verilog) of user_clk_sel.u_jhmkpjjmdkx(jhmkpjjmdkx)
@W:MO129 : initcfg_xf.v(28) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.bmnfdkrhvvn has been reduced to a combinational gate by constant propagation
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 48MB)
Encoding state machine work.ccfdxrhchsz_Z1(verilog)-frcskdnwvmx[11:0]
original code -> new code
   0000 -> 000000000001
   0001 -> 000000000010
   0010 -> 000000000100
   0011 -> 000000001000
   0100 -> 000000010000
   0101 -> 000000100000
   0110 -> 000001000000
   0111 -> 000010000000
   1000 -> 000100000000
   1001 -> 001000000000
   1010 -> 010000000000
   1011 -> 100000000000
@N:MF176 :  | Default generator successful  
Encoding state machine work.nbnjbfrkqwq_Z2(verilog)-tkcbxxqbtfx[17:0]
original code -> new code
   00000 -> 000000000000000001
   00001 -> 000000000000000010
   00010 -> 000000000000000100
   00011 -> 000000000000001000
   00100 -> 000000000000010000
   00101 -> 000000000000100000
   00110 -> 000000000001000000
   00111 -> 000000000010000000
   01000 -> 000000000100000000
   01001 -> 000000001000000000
   01010 -> 000000010000000000
   01011 -> 000000100000000000
   01100 -> 000001000000000000
   01101 -> 000010000000000000
   01110 -> 000100000000000000
   01111 -> 001000000000000000
   10000 -> 010000000000000000
   10001 -> 100000000000000000
@N:MF176 :  | Default generator successful  
@N:MF176 :  | Default generator successful  
@N:MF238 : smev.v(152) | Found 5 bit incrementor, 'un6_ckghxwbsztp[4:0]'
@N:MF179 : smev.v(141) | Found 12 bit by 12 bit '<' comparator, 'pvtdpmmqdpp.pbzxzjhqhwz'
Encoding state machine work.fmvgpwbdcxs_Z3(verilog)-jzzdfrmzwdj[15:0]
original code -> new code
   0000 -> 0000000000000001
   0001 -> 0000000000000010
   0010 -> 0000000000000100
   0011 -> 0000000000001000
   0100 -> 0000000000010000
   0101 -> 0000000000100000
   0110 -> 0000000001000000
   0111 -> 0000000010000000
   1000 -> 0000000100000000
   1001 -> 0000001000000000
   1010 -> 0000010000000000
   1011 -> 0000100000000000
   1100 -> 0001000000000000
   1101 -> 0010000000000000
   1110 -> 0100000000000000
   1111 -> 1000000000000000
@N:MF176 :  | Default generator successful  
Encoding state machine work.stnpfdkggvx_4s_2s_0_1_2_3_4_5_6_7(verilog)-mwtvnzdkmwm[7:0]
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
Encoding state machine work.wbsfnwwctpn_Z5(verilog)-crpwsdfhcqq[8:0]
original code -> new code
   0000 -> 000000001
   0001 -> 000000010
   0010 -> 000000100
   0011 -> 000001000
   0100 -> 000010000
   0101 -> 000100000
   0110 -> 001000000
   0111 -> 010000000
   1000 -> 100000000
@W:MO129 : initcfg_xb.v(56) | Sequential instance NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[2] has been reduced to a combinational gate by constant propagation
@N:MF176 :  | Default generator successful  
@N:MF176 :  | Default generator successful  
@W:MO129 : initcfg_xf.v(31) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.zmbsbbtjszd has been reduced to a combinational gate by constant propagation
Automatic dissolve during optimization of view:work.dxwqxgdccxc_9s(verilog) of dkjzqmrkvwb_d1(ADD_13_const_6)
Auto Dissolve of dkjzqmrkvwb_d0 (inst of view:VhdlGenLib.ADD_13_const_5(verilog))
Auto Dissolve of user_control.u_ffppvfwnggt (inst of view:work.ffppvfwnggt_4s_2s_9s(verilog))

Finished factoring (Time elapsed 0h:00m:04s; Memory used current: 53MB peak: 54MB)
@W:BN116 : initcfg_xb.v(49) | Removing sequential instance NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[0] of view:PrimLib.dffs(prim) because there are no references to its outputs 
@W:BN116 : assc.v(187) | Removing sequential instance Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.ssssgmdwsms of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : assc.v(248) | Removing sequential instance Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.cqxzbmfvwmz of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[3] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[5] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[6] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[7] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[8] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[9] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[10] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[11] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[12] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[13] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[16] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[17] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[18] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[19] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[24] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[25] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[26] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[27] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[28] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[29] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[30] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.v(91) | Removing sequential instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.mwzbqqvzwjt[31] of view:PrimLib.dffr(prim) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:04s; Memory used current: 51MB peak: 54MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:05s; Memory used current: 54MB peak: 54MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:05s; Memory used current: 54MB peak: 55MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:06s; Memory used current: 53MB peak: 56MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:06s; Memory used current: 53MB peak: 56MB)

Finished preparing to map (Time elapsed 0h:00m:07s; Memory used current: 58MB peak: 58MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name                                                                                                                       Fanout, notes                   
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.jzzdfrmzwdj[3] / Q                                                   13                              
NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.address_gen.u_dxwqxgdccxc.gnmdxrqrdgs[7] / Q                          13                              
NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.user_clk_sel.u_jhmkpjjmdkx.hrgmtcpsdzr / Q                            87                              
NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.user_control.u_ffppvfwnggt.jsnhqgkgbcr.un1_sdcfzkxtrzd_1_i_o2 / Y     18                              
Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0 / DOUTB8                                                                                   13                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.xwhwqsjfmgh / Q                                                      15                              
Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0 / DOUTB6                                                                                   13                              
Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0 / DOUTB8                                                                                   15                              
Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.jzzdfrmzwdj[1] / Q                                                   17                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[0] / Q                                                   36                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[1] / Q                                                   36                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[2] / Q                                                   36                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[3] / Q                                                   73                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rgmpzqrbghh / Q                                                      18                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.tkcbxxqbtfx[13] / Q                                                  29                              
Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.tkcbxxqbtfx[9] / Q                                                   13                              
Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.frcskdnwvmx[3] / Q                                                   14                              
SYS_RESET_pad / Y                                                                                                                                244 : 239 asynchronous set/reset
NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.user_control.u_ffppvfwnggt.hrdbnmzftpn_0_o2[12] / Y                   13                              
Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.jzzdfrmzwdj_ns_i_0_tz[7] / Y                                         15                              
=================================================================================================================================================================================

Promoting Net SYS_RESET_c on CLKBUF  SYS_RESET_pad
Promoting Net INIT_DONE_net on CLKINT  I_105
Promoting Net Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[3] on CLKINT  I_106
Replicating Combinational Instance Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.jzzdfrmzwdj_ns_i_0_tz[7], fanout 15 segments 2
Replicating Combinational Instance NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.user_control.u_ffppvfwnggt.hrdbnmzftpn_0_o2[12], fanout 13 segments 2
Replicating Sequential Instance Analog_inst.Analog_smtr_wrapper_inst.user_Analog_smtr_wrapper.u_ccfdxrhchsz.frcskdnwvmx[3], fanout 14 segments 2
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.tkcbxxqbtfx[9], fanout 13 segments 2
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.tkcbxxqbtfx[13], fanout 29 segments 3
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rgmpzqrbghh, fanout 18 segments 2
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[2], fanout 36 segments 3
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[1], fanout 36 segments 3
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.rdgwgtpkbgc[0], fanout 36 segments 3
Replicating Sequential Instance Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.jzzdfrmzwdj[1], fanout 17 segments 2
Buffering Analog_inst.un1_Analog_smev_ram_inst_1[8], fanout 15 segments 2
Buffering Analog_inst.un1_Analog_smev_ram_inst_1[6], fanout 13 segments 2
Replicating Sequential Instance Analog_inst.Analog_smev_wrapper_inst.user_Analog_smev_wrapper.u_nbnjbfrkqwq.xwhwqsjfmgh, fanout 15 segments 2
Buffering Analog_inst.un1_Analog_smtr_ram_inst_1[8], fanout 13 segments 2
Replicating Combinational Instance NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.user_control.u_ffppvfwnggt.jsnhqgkgbcr.un1_sdcfzkxtrzd_1_i_o2, fanout 18 segments 2
Replicating Sequential Instance NVM_inst.NVM_sys_init_wrapper_inst.user_NVM_sys_init_wrapper.u_grwzcnqmqzm.address_gen.u_dxwqxgdccxc.gnmdxrqrdgs[7], fanout 13 segments 2
Replicating Sequential Instance Analog_inst.Analog_assc_wrapper_inst.user_Analog_assc_wrapper.u_fmvgpwbdcxs.jzzdfrmzwdj[3], fanout 13 segments 2

Finished technology mapping (Time elapsed 0h:00m:08s; Memory used current: 63MB peak: 65MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:08s; Memory used current: 63MB peak: 65MB)

Added 3 Buffers
Added 18 Cells via replication
	Added 15 Sequential Cells via replication
	Added 3 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:08s; Memory used current: 63MB peak: 65MB)
Writing Analyst data base D:\Actelprj\VT_Mon_vlog\synthesis\VT_Mon.srm
@N:BN225 :  | Writing default property annotation file D:\Actelprj\VT_Mon_vlog\synthesis\VT_Mon.map. 
Writing EDIF Netlist and constraint files
Found clock VT_Mon|PLL_inst.CLK10M_inferred_clock with period 10.00ns 
Found clock VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Mar 01 15:18:47 2007
#


Top view:               VT_Mon
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N:MT195 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT197 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: -11.524

                                                 Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                                   Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------------------------
VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     100.0 MHz     46.5 MHz      10.000        21.524        -11.524     inferred     Inferred_clkgroup_0
=====================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                      |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                      Ending                                        |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock  VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock  |  10.000      -11.524  |  No paths    -      |  No paths    -      |  No paths    -    
VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock  VT_Mon|PLL_inst.CLK10M_inferred_clock         |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                      Starting                                                                                 Arrival            
Instance              Reference                                        Type     Pin       Net                  Time        Slack  
                      Clock                                                                                                       
----------------------------------------------------------------------------------------------------------------------------------
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[1]     INIT_DATA_net[1]     19.821      -11.524
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[2]     INIT_DATA_net[2]     19.794      -11.498
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[0]     INIT_DATA_net[0]     19.781      -11.485
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[3]     INIT_DATA_net[3]     19.664      -11.367
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[4]     INIT_DATA_net[4]     19.651      -11.354
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[5]     INIT_DATA_net[5]     19.585      -11.288
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[6]     INIT_DATA_net[6]     19.559      -11.262
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[7]     INIT_DATA_net[7]     19.559      -11.262
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      RD[8]     INIT_DATA_net[8]     19.677      -11.240
NVM_inst.NVM_INST     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     NVM      BUSY      NVM_BUSY_net         9.229       -8.046 
==================================================================================================================================


Ending Points with Worst Slack
******************************

                                                          Starting                                                                                   Required            
Instance                                                  Reference                                        Type       Pin       Net                  Time         Slack  
                                                          Clock                                                                                                          
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA1     INIT_DATA_net[1]     8.930        -11.524
Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA1     INIT_DATA_net[1]     8.930        -11.524
Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA1     INIT_DATA_net[1]     8.930        -11.524
Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA2     INIT_DATA_net[2]     8.930        -11.498
Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA2     INIT_DATA_net[2]     8.930        -11.498
Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA2     INIT_DATA_net[2]     8.930        -11.498
Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA0     INIT_DATA_net[0]     8.930        -11.485
Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA0     INIT_DATA_net[0]     8.930        -11.485
Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA0     INIT_DATA_net[0]     8.930        -11.485
Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0     VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock     RAM4K9     DINA3     INIT_DATA_net[3]     8.930        -11.367
=========================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst (RTL View)
View Worst Path in Analyst (Tech View)
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      20.454
    = Slack (critical) :                     -11.524

    Number of logic level(s):                0
    Starting point:                          NVM_inst.NVM_INST / RD[1]
    Ending point:                            Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0 / DINA1
    The start point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLK
    The end   point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLKA

Instance / Net                                                       Pin       Pin                Arrival     No. of    
Name                                                      Type       Name      Dir     Delay      Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
NVM_inst.NVM_INST                                         NVM        RD[1]     Out     19.821     19.821      -         
INIT_DATA_net[1]                                          Net        -         -       0.633      -           4         
Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0     RAM4K9     DINA1     In      -          20.454      -         
========================================================================================================================
Total path delay (propagation time + setup) of 21.524 is 20.891(97.1%) logic and 0.633(2.9%) route.


Path information for path number 2: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      20.454
    = Slack (critical) :                     -11.524

    Number of logic level(s):                0
    Starting point:                          NVM_inst.NVM_INST / RD[1]
    Ending point:                            Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0 / DINA1
    The start point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLK
    The end   point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLKA

Instance / Net                                                       Pin       Pin                Arrival     No. of    
Name                                                      Type       Name      Dir     Delay      Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
NVM_inst.NVM_INST                                         NVM        RD[1]     Out     19.821     19.821      -         
INIT_DATA_net[1]                                          Net        -         -       0.633      -           4         
Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0     RAM4K9     DINA1     In      -          20.454      -         
========================================================================================================================
Total path delay (propagation time + setup) of 21.524 is 20.891(97.1%) logic and 0.633(2.9%) route.


Path information for path number 3: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      20.454
    = Slack (critical) :                     -11.524

    Number of logic level(s):                0
    Starting point:                          NVM_inst.NVM_INST / RD[1]
    Ending point:                            Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0 / DINA1
    The start point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLK
    The end   point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLKA

Instance / Net                                                       Pin       Pin                Arrival     No. of    
Name                                                      Type       Name      Dir     Delay      Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
NVM_inst.NVM_INST                                         NVM        RD[1]     Out     19.821     19.821      -         
INIT_DATA_net[1]                                          Net        -         -       0.633      -           4         
Analog_inst.Analog_smev_ram_inst.Analog_smev_ram_R0C0     RAM4K9     DINA1     In      -          20.454      -         
========================================================================================================================
Total path delay (propagation time + setup) of 21.524 is 20.891(97.1%) logic and 0.633(2.9%) route.


Path information for path number 4: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      20.428
    = Slack (non-critical) :                 -11.498

    Number of logic level(s):                0
    Starting point:                          NVM_inst.NVM_INST / RD[2]
    Ending point:                            Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0 / DINA2
    The start point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLK
    The end   point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLKA

Instance / Net                                                       Pin       Pin                Arrival     No. of    
Name                                                      Type       Name      Dir     Delay      Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
NVM_inst.NVM_INST                                         NVM        RD[2]     Out     19.794     19.794      -         
INIT_DATA_net[2]                                          Net        -         -       0.633      -           4         
Analog_inst.Analog_assc_ram_inst.Analog_assc_ram_R0C0     RAM4K9     DINA2     In      -          20.428      -         
========================================================================================================================
Total path delay (propagation time + setup) of 21.498 is 20.865(97.1%) logic and 0.633(2.9%) route.


Path information for path number 5: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      20.428
    = Slack (non-critical) :                 -11.498

    Number of logic level(s):                0
    Starting point:                          NVM_inst.NVM_INST / RD[2]
    Ending point:                            Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0 / DINA2
    The start point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLK
    The end   point is clocked by            VT_Mon|NGMUX_inst.SYS_CLK_int_inferred_clock [rising] on pin CLKA

Instance / Net                                                       Pin       Pin                Arrival     No. of    
Name                                                      Type       Name      Dir     Delay      Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------
NVM_inst.NVM_INST                                         NVM        RD[2]     Out     19.794     19.794      -         
INIT_DATA_net[2]                                          Net        -         -       0.633      -           4         
Analog_inst.Analog_smtr_ram_inst.Analog_smtr_ram_R0C0     RAM4K9     DINA2     In      -          20.428      -         
========================================================================================================================
Total path delay (propagation time + setup) of 21.498 is 20.865(97.1%) logic and 0.633(2.9%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell VT_Mon.verilog
  Core Cell usage:
              cell count     area count*area
              AND2     7      1.0        7.0
             AND2A     3      1.0        3.0
              AND3     4      1.0        4.0
               AO1    29      1.0       29.0
              AO13     1      1.0        1.0
              AO18     5      1.0        5.0
              AO1A     6      1.0        6.0
              AO1B    31      1.0       31.0
              AO1C    13      1.0       13.0
              AO1D     4      1.0        4.0
              AOI1     5      1.0        5.0
             AOI1A     5      1.0        5.0
             AOI1B    29      1.0       29.0
               AX1     1      1.0        1.0
              AX1A     1      1.0        1.0
              AX1B     9      1.0        9.0
              AX1C    11      1.0       11.0
              AX1D     4      1.0        4.0
              AX1E     1      1.0        1.0
              BUFF     3      1.0        3.0
            CLKINT     2      0.0        0.0
               GND    32      0.0        0.0
               INV     3      1.0        3.0
              MIN3     1      1.0        1.0
               MX2   200      1.0      200.0
              MX2A     8      1.0        8.0
              MX2B     4      1.0        4.0
              MX2C    21      1.0       21.0
             NGMUX     1      1.0        1.0
              NOR2    31      1.0       31.0
             NOR2A   106      1.0      106.0
             NOR2B   119      1.0      119.0
              NOR3     7      1.0        7.0
             NOR3A    27      1.0       27.0
             NOR3B    19      1.0       19.0
             NOR3C    22      1.0       22.0
               OA1    15      1.0       15.0
              OA1A    31      1.0       31.0
              OA1B     5      1.0        5.0
              OA1C     5      1.0        5.0
              OAI1     3      1.0        3.0
               OR2    34      1.0       34.0
              OR2A    41      1.0       41.0
              OR2B    59      1.0       59.0
               OR3    21      1.0       21.0
              OR3A    15      1.0       15.0
              OR3B    33      1.0       33.0
              OR3C    19      1.0       19.0
               PLL     1      0.0        0.0
               VCC    32      0.0        0.0
              XA1A     7      1.0        7.0
              XA1B     1      1.0        1.0
              XA1C     1      1.0        1.0
              XAI1     1      1.0        1.0
             XAI1A     3      1.0        3.0
             XNOR2    24      1.0       24.0
             XNOR3    17      1.0       17.0
              XO1A     2      1.0        2.0
              XOR2    51      1.0       51.0
              XOR3     2      1.0        2.0
              ZOR3     1      1.0        1.0


            DFN1C0   130      1.0      130.0
          DFN1E0C0    26      1.0       26.0
          DFN1E1C0    89      1.0       89.0
            DFN1P0     9      1.0        9.0
               NVM     1      0.0        0.0
            RAM4K9     3      0.0        0.0
                   -----          ----------
             TOTAL  1457              1386.0


  IO Cell usage:
              cell count
                AB     1
            CLKBUF     1
             INBUF     2
           INBUF_A     3
          OUTBUF_A     2
                   -----
             TOTAL     9


Combinational Cells: 1132
Sequential Cells   : 254
IO Cells           : 9
Mapper successful!
Process took 0h:00m:11s realtime, 0h:00m:09s cputime
# Thu Mar 01 15:18:47 2007

###########################################################]