#Build: Synplify Pro 8.5B, Build 429R, Dec  8 2005
#install: D:\Libero71\Synplify\Synplify_85B
#OS: Windows XP 5.1
#Hostname: WXP-ALIM

#Thu May 18 12:33:30 2006

$ Start of Compile
#Thu May 18 12:33:30 2006

Synplicity VHDL Compiler, version 3.4.1, Build 089R, built Mar  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@N: : my_top.vhd(8) | Top entity is set to my_TOP.
VHDL syntax check successful!
File G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_rev2\hdl\voltage_seq_control.vhd changed - recompiling
@N:CD630 : my_top.vhd(7) | Synthesizing work.my_top.def_arch 
@W:CD639 : my_top.vhd(118) | Bit <0> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <1> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <2> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <3> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <4> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <5> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <6> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(118) | Bit <7> of signal init_addr_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <0> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <1> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <2> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <3> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <4> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <5> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <6> of signal init_data_int is undriven 
@W:CD639 : my_top.vhd(124) | Bit <7> of signal init_data_int is undriven 
@W:CD638 : my_top.vhd(132) | Signal acn5p0v_over1p5a_int is undriven 
@N:CD630 : fusion.vhd(1660) | Synthesizing work.dfn1c0.syn_black_box 
Post processing for work.dfn1c0.syn_black_box
@N:CD630 : fusion.vhd(3554) | Synthesizing work.mx2.syn_black_box 
Post processing for work.mx2.syn_black_box
@N:CD630 : voltage_n50_50_33_15.vhd(7) | Synthesizing work.voltage_n50_50_33_15.def_arch 
@N:CD630 : fusion.vhd(5552) | Synthesizing work.ab.syn_black_box 
Post processing for work.ab.syn_black_box
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <0> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <1> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <2> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <3> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <4> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <5> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <6> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(246) | Bit <7> of signal assc_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <0> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <1> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <2> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <3> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <4> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <5> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <6> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(252) | Bit <7> of signal assc_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <0> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <1> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <2> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <3> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <4> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <5> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <6> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(258) | Bit <7> of signal assc_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <0> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <1> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <2> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <3> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <4> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <5> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <6> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(264) | Bit <7> of signal assc_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <0> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <1> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <2> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <3> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <4> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <5> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <6> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(270) | Bit <7> of signal assc_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(276) | Bit <0> of signal adc_mode_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(276) | Bit <1> of signal adc_mode_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(276) | Bit <2> of signal adc_mode_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(279) | Bit <0> of signal adc_chnr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(279) | Bit <1> of signal adc_chnr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(279) | Bit <2> of signal adc_chnr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(279) | Bit <3> of signal adc_chnr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <0> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <1> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <2> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <3> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <4> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <5> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(282) | Bit <6> of signal adc_stc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <0> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <1> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <2> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <3> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <4> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <5> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(286) | Bit <6> of signal adc_tvc_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <0> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <1> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <2> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <3> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <4> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <5> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <6> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <7> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <8> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <9> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(291) | Bit <10> of signal adc_result_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <0> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <1> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <2> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <3> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <4> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <5> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <6> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(304) | Bit <7> of signal ev_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <0> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <1> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <2> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <3> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <4> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <5> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <6> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(309) | Bit <7> of signal ev_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <0> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <1> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <2> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <3> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <4> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <5> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <6> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(315) | Bit <7> of signal ev_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <0> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <1> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <2> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <3> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <4> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <5> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <6> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(320) | Bit <7> of signal ev_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <0> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <1> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <2> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <3> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <4> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <5> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <6> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(326) | Bit <7> of signal ev_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <0> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <1> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <2> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <3> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <4> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <5> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <6> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(331) | Bit <7> of signal ev_asscaddr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(337) | Bit <0> of signal assc_seqout_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(337) | Bit <1> of signal assc_seqout_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(337) | Bit <2> of signal assc_seqout_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(337) | Bit <3> of signal assc_seqout_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(337) | Bit <4> of signal assc_seqout_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <0> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <1> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <2> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <3> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <4> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <5> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <6> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(343) | Bit <7> of signal assc_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <0> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <1> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <2> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <3> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <4> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <5> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <6> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(349) | Bit <7> of signal tr_ev_addr_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(355) | Bit <0> of signal ev_chhold_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(355) | Bit <1> of signal ev_chhold_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(355) | Bit <2> of signal ev_chhold_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(355) | Bit <3> of signal ev_chhold_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <0> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <1> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <2> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <3> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <4> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <5> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <6> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(359) | Bit <7> of signal ev_ram_do_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <0> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <1> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <2> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <3> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <4> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <5> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <6> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(365) | Bit <7> of signal tr_ram_di_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <0> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <1> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <2> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <3> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <4> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <5> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <6> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(370) | Bit <7> of signal tr_ram_addr_a_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <0> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <1> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <2> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <3> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <4> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <5> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <6> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(376) | Bit <7> of signal tr_ram_di_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <0> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <1> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <2> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <3> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <4> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <5> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <6> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(381) | Bit <7> of signal tr_ram_addr_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <0> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <1> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <2> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <3> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <4> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <5> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <6> of signal tr_ram_do_b_net is undriven 
@W:CD639 : voltage_n50_50_33_15.vhd(387) | Bit <7> of signal tr_ram_do_b_net is undriven 
@N:CD630 : fusion.vhd(4606) | Synthesizing work.vcc.syn_black_box 
Post processing for work.vcc.syn_black_box
@N:CD630 : fusion.vhd(2020) | Synthesizing work.gnd.syn_black_box 
Post processing for work.gnd.syn_black_box
@N:CD630 : voltage_n50_50_33_15_assc_ram.vhd(7) | Synthesizing work.voltage_n50_50_33_15_assc_ram.def_arch 
@N:CD630 : fusion.vhd(5075) | Synthesizing work.ram4k9.syn_black_box 
Post processing for work.ram4k9.syn_black_box
Post processing for work.voltage_n50_50_33_15_assc_ram.def_arch
@N:CD630 : fusion.vhd(2026) | Synthesizing work.inbuf_a.syn_black_box 
Post processing for work.inbuf_a.syn_black_box
@N:CD630 : voltage_n50_50_33_15_smtr_ram.vhd(7) | Synthesizing work.voltage_n50_50_33_15_smtr_ram.def_arch 
Post processing for work.voltage_n50_50_33_15_smtr_ram.def_arch
@N:CD630 : fusion.vhd(3755) | Synthesizing work.or2.syn_black_box 
Post processing for work.or2.syn_black_box
@N:CD630 : voltage_n50_50_33_15_smev_ram.vhd(7) | Synthesizing work.voltage_n50_50_33_15_smev_ram.def_arch 
Post processing for work.voltage_n50_50_33_15_smev_ram.def_arch
@N:CD630 : voltage_n50_50_33_15_smtr_wrapper.vhd(75) | Synthesizing work.voltage_n50_50_33_15_smtr_wrapper.def_arch 
@N:CD630 : smtr.vhd(283) | Synthesizing work.smtr.behv 
@N:CD630 : smtr.vhd(10) | Synthesizing work.ccfdxrhchsz.djzfpsxghmt 
@N:CD231 : smtr.vhd(62) | Using onehot encoding for type bzhvcjnmprc (tddtwhmsmxw="100000000000")
@W:CD638 : smtr.vhd(72) | Signal jjnnjkrjzfq is undriven 
@W:CD638 : smtr.vhd(77) | Signal mgqspspvvwp is undriven 
@W:CD638 : smtr.vhd(86) | Signal czjszchcxth is undriven 
@W:CD638 : smtr.vhd(91) | Signal rdqhbcjchvq is undriven 
Post processing for work.ccfdxrhchsz.djzfpsxghmt
@N:CL201 : smtr.vhd(254) | Trying to extract state machine for register frcskdnwvmx
Extracted state machine for register frcskdnwvmx
State machine has 12 reachable states with original encodings of:
   000000000001
   000000000010
   000000000100
   000000001000
   000000010000
   000000100000
   000001000000
   000010000000
   000100000000
   001000000000
   010000000000
   100000000000
@W:CL234 : smtr.vhd(21) | Input port bits <8 to 1> of qxzrwpjhcww(8 downto 0) are unused 
@W:CL159 : smtr.vhd(19) | Input qbrqxpmkpsw is unused
@W:CL159 : smtr.vhd(19) | Input nktsnhmjrbx is unused
@W:CL159 : smtr.vhd(22) | Input dnmrkvrtbjn is unused
Post processing for work.smtr.behv
Post processing for work.voltage_n50_50_33_15_smtr_wrapper.def_arch
@N:CD630 : fusion.vhd(3815) | Synthesizing work.outbuf_a.syn_black_box 
Post processing for work.outbuf_a.syn_black_box
@N:CD630 : voltage_n50_50_33_15_assc_wrapper.vhd(115) | Synthesizing work.voltage_n50_50_33_15_assc_wrapper.def_arch 
@N:CD630 : assc.vhd(374) | Synthesizing work.assc.behv 
@N:CD630 : assc.vhd(10) | Synthesizing work.cwgmnvwgkwq.wzrwkfmxjkf 
@N:CD231 : assc.vhd(80) | Using onehot encoding for type bzrdgxjrssj (zhnxfbzxsbj="100000000000000")
Post processing for work.cwgmnvwgkwq.wzrwkfmxjkf
@W:CL169 : assc.vhd(315) | Pruning Register pbpfdkhvxdb  
@W:CL169 : assc.vhd(315) | Pruning Register dvpgmbcxcxr(10 downto 0)  
@W:CL170 : assc.vhd(301) | Pruning bit <9> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <8> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <7> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <6> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <5> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <4> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <3> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@W:CL170 : assc.vhd(301) | Pruning bit <2> of hxjrdtjfjrt(9 downto 0) - not in use ... 
@N:CL201 : assc.vhd(294) | Trying to extract state machine for register zwnnqcvfccb
Extracted state machine for register zwnnqcvfccb
State machine has 15 reachable states with original encodings of:
   000000000000001
   000000000000010
   000000000000100
   000000000001000
   000000000010000
   000000000100000
   000000001000000
   000000010000000
   000000100000000
   000001000000000
   000010000000000
   000100000000000
   001000000000000
   010000000000000
   100000000000000
@W:CL159 : assc.vhd(18) | Input cnwsmzznwfg is unused
@W:CL159 : assc.vhd(19) | Input npqxxjzzczt is unused
Post processing for work.assc.behv
Post processing for work.voltage_n50_50_33_15_assc_wrapper.def_arch
@N:CD630 : voltage_n50_50_33_15_smev_wrapper.vhd(83) | Synthesizing work.voltage_n50_50_33_15_smev_wrapper.def_arch 
@N:CD630 : smev.vhd(308) | Synthesizing work.smev.behv 
@N:CD630 : smev.vhd(10) | Synthesizing work.nbnjbfrkqwq.qhrkzzskhwz 
@N:CD231 : smev.vhd(61) | Using onehot encoding for type vspwsmpffhb (kntgqgfbzkr="100000000000000000")
@W:CD638 : smev.vhd(77) | Signal smsgrfvbrts is undriven 
Post processing for work.nbnjbfrkqwq.qhrkzzskhwz
@N:CL201 : smev.vhd(247) | Trying to extract state machine for register tkcbxxqbtfx
Extracted state machine for register tkcbxxqbtfx
State machine has 18 reachable states with original encodings of:
   000000000000000001
   000000000000000010
   000000000000000100
   000000000000001000
   000000000000010000
   000000000000100000
   000000000001000000
   000000000010000000
   000000000100000000
   000000001000000000
   000000010000000000
   000000100000000000
   000001000000000000
   000010000000000000
   000100000000000000
   001000000000000000
   010000000000000000
   100000000000000000
@W:CL159 : smev.vhd(19) | Input zxrxtxxbsks is unused
@W:CL159 : smev.vhd(19) | Input zhkvvfnsbjb is unused
@W:CL159 : smev.vhd(24) | Input mqmgjkmdztb is unused
Post processing for work.smev.behv
Post processing for work.voltage_n50_50_33_15_smev_wrapper.def_arch
Post processing for work.voltage_n50_50_33_15.def_arch
@N:CD630 : fusion.vhd(2236) | Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
@N:CD630 : voltage_seq_control.vhd(5) | Synthesizing work.voltage_seq_control.def_arch 
@N:CD231 : voltage_seq_control.vhd(55) | Using onehot encoding for type state_type (warmup="100000000000000")
@N:CD630 : count12.vhd(6) | Synthesizing work.count12.behavioral 
Post processing for work.count12.behavioral
Post processing for work.voltage_seq_control.def_arch
@W:CL169 : voltage_seq_control.vhd(88) | Pruning Register aclr_cntr  
@W:CL168 : voltage_seq_control.vhd(77) | Pruning instance my_count - not in use ... 
@W:CL112 : voltage_seq_control.vhd(88) | Feedback mux created for signal all_supply_on. Did you forget the set/reset assignment for this signal?
@W:CL112 : voltage_seq_control.vhd(88) | Feedback mux created for signal all_load_on. Did you forget the set/reset assignment for this signal?
@N:CL201 : voltage_seq_control.vhd(88) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 15 reachable states with original encodings of:
   000000000000001
   000000000000010
   000000000000100
   000000000001000
   000000000010000
   000000000100000
   000000001000000
   000000010000000
   000000100000000
   000001000000000
   000010000000000
   000100000000000
   001000000000000
   010000000000000
   100000000000000
@W:CL159 : voltage_seq_control.vhd(23) | Input acn5p0v_over1p5a is unused
@W:CL159 : voltage_seq_control.vhd(28) | Input ac5p0v_ac5p0v_over2p0a is unused
@N:CD630 : nvm_init.vhd(7) | Synthesizing work.nvm_init.def_arch 
@N:CD630 : fusion.vhd(5721) | Synthesizing work.nvm.syn_black_box 
Post processing for work.nvm.syn_black_box
@W:CD639 : nvm_init.vhd(85) | Bit <0> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <1> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <2> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <3> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <4> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <5> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <6> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <7> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <8> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <9> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <10> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <11> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <12> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <13> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <14> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <15> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <16> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <17> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <18> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <19> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <20> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <21> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <22> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <23> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <24> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <25> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <26> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <27> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <28> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <29> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(85) | Bit <30> of signal nvm_dat_to_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <0> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <1> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <2> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <3> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <4> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <5> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <6> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <7> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <8> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <9> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <10> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <11> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <12> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <13> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <14> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <15> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(102) | Bit <16> of signal nvm_add_net is undriven 
@W:CD639 : nvm_init.vhd(110) | Bit <0> of signal nvm_width_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <0> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <1> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <2> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <3> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <4> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <5> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <6> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <7> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <8> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <9> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <10> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <11> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <12> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <13> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <14> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <15> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <16> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <17> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <18> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <19> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <20> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <21> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <22> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <23> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <24> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <25> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <26> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <27> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <28> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <29> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(117) | Bit <30> of signal nvm_dat_from_net is undriven 
@W:CD639 : nvm_init.vhd(134) | Bit <0> of signal nvm_status_net is undriven 
@N:CD630 : nvm_init_init_wrapper.vhd(127) | Synthesizing work.nvm_init_init_wrapper.def_arch 
@N:CD630 : initcfg.vhd(585) | Synthesizing work.initcfg.behavior 
@N:CD630 : initcfg.vhd(10) | Synthesizing work.grwzcnqmqzm.mjtkskcsjhk 
@N:CD630 : initcfg_xf.vhd(37) | Synthesizing work.initcfg_xf.behavior 
@N:CD630 : initcfg_xf.vhd(10) | Synthesizing work.jhmkpjjmdkx.bmnqpbgpmvq 
Post processing for work.jhmkpjjmdkx.bmnqpbgpmvq
Post processing for work.initcfg_xf.behavior
@N:CD630 : initcfg_xe.vhd(27) | Synthesizing work.initcfg_xe.behavior 
@N:CD630 : initcfg_xe.vhd(10) | Synthesizing work.gpbdjfttbjd.zsftcmnmkdb 
Post processing for work.gpbdjfttbjd.zsftcmnmkdb
Post processing for work.initcfg_xe.behavior
@N:CD630 : initcfg_xd.vhd(56) | Synthesizing work.initcfg_xd.behavior 
@N:CD630 : initcfg_xd.vhd(10) | Synthesizing work.dxwqxgdccxc.cmvhvtvbzkh 
Post processing for work.dxwqxgdccxc.cmvhvtvbzkh
Post processing for work.initcfg_xd.behavior
@N:CD630 : initcfg_xc.vhd(155) | Synthesizing work.initcfg_xc.behavior 
@N:CD630 : initcfg_xc.vhd(10) | Synthesizing work.ffppvfwnggt.zgctkkxfnjk 
Post processing for work.ffppvfwnggt.zgctkkxfnjk
Post processing for work.initcfg_xc.behavior
@N:CD630 : initcfg_xb.vhd(70) | Synthesizing work.initcfg_xb.behavior 
@N:CD630 : initcfg_xb.vhd(11) | Synthesizing work.wbsfnwwctpn.mmwvfpfbppr 
@N:CD231 : initcfg_xb.vhd(23) | Using onehot encoding for type cjhswcdjptj (cqppqjpknwn="100000000")
Post processing for work.wbsfnwwctpn.mmwvfpfbppr
@N:CL201 : initcfg_xb.vhd(47) | Trying to extract state machine for register crpwsdfhcqq
Extracted state machine for register crpwsdfhcqq
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
Post processing for work.initcfg_xb.behavior
@N:CD630 : initcfg_xa.vhd(57) | Synthesizing work.initcfg_xa.behavior 
@N:CD630 : initcfg_xa.vhd(11) | Synthesizing work.stnpfdkggvx.zkzbcmxmrjf 
@N:CD231 : initcfg_xa.vhd(21) | Using onehot encoding for type bfjbqwgdgfk (tvzdqnwfvfh="10000000")
Post processing for work.stnpfdkggvx.zkzbcmxmrjf
@N:CL201 : initcfg_xa.vhd(41) | Trying to extract state machine for register mwtvnzdkmwm
Extracted state machine for register mwtvnzdkmwm
State machine has 8 reachable states with original encodings of:
   00000001
   00000010
   00000100
   00001000
   00010000
   00100000
   01000000
   10000000
Post processing for work.initcfg_xa.behavior
Post processing for work.grwzcnqmqzm.mjtkskcsjhk
Post processing for work.initcfg.behavior
Post processing for work.nvm_init_init_wrapper.def_arch
Post processing for work.nvm_init.def_arch
@W:CL168 : nvm_init.vhd(404) | Pruning instance VCC_power_inst1 - not in use ... 
Post processing for work.my_top.def_arch
@W:CL167 : my_top.vhd(167) | Input acn5p0v_over1p5a of instance MY_VOLTAGE_SEQ is floating
@W:CL167 : my_top.vhd(167) | Input ac5p0v_ac5p0v_over2p0a of instance MY_VOLTAGE_SEQ is floating
@END
Process took 0h:00m:07s realtime, 0h:00m:07s cputime
# Thu May 18 12:33:37 2006

###########################################################[
Synplicity Proasic Technology Mapper, Version 8.4.0.p, Build 075R, Built Mar  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.5B
@W:BN227 :  | This data was produced by a restricted version of Synplicity software. The results contain Synplicity IP and are not licensed to be used for production design work or design services 
@N:MF249 :  | Running in 32-bit mode. 
@N: :  | Gated clock conversion disabled  
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 


Automatic dissolve at startup in view:work.INITCFG_XF(behavior) of u_jhmkpjjmdkx(jhmkpjjmdkx)
Automatic dissolve at startup in view:work.grwzcnqmqzm(mjtkskcsjhk) of user_clk_sel(INITCFG_XF)
Automatic dissolve at startup in view:work.voltage_n50_50_33_15(def_arch) of voltage_n50_50_33_15_assc_ram_inst(voltage_n50_50_33_15_assc_ram)
Automatic dissolve at startup in view:work.voltage_n50_50_33_15(def_arch) of voltage_n50_50_33_15_smtr_ram_inst(voltage_n50_50_33_15_smtr_ram)
Automatic dissolve at startup in view:work.voltage_n50_50_33_15(def_arch) of voltage_n50_50_33_15_smev_ram_inst(voltage_n50_50_33_15_smev_ram)
@W:MO129 : initcfg_xf.vhd(29) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.bmnfdkrhvvn has been reduced to a combinational gate by constant propagation
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 32MB)
Encoding state machine work.stnpfdkggvx(zkzbcmxmrjf)-mwtvnzdkmwm[0:7]
original code -> new code
   00000001 -> 00000001
   00000010 -> 00000010
   00000100 -> 00000100
   00001000 -> 00001000
   00010000 -> 00010000
   00100000 -> 00100000
   01000000 -> 01000000
   10000000 -> 10000000
Encoding state machine work.wbsfnwwctpn(mmwvfpfbppr)-crpwsdfhcqq[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
@W:MO129 : initcfg_xb.vhd(47) | Sequential instance NVM_BLK.nvm_init_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.qmdjrgthbvj has been reduced to a combinational gate by constant propagation
@N:MF176 :  | Default generator successful  
@N:MF176 :  | Default generator successful  
@N:MF176 :  | Default generator successful  
Encoding state machine work.voltage_seq_control(def_arch)-state[0:14]
original code -> new code
   000000000000001 -> 000000000000001
   000000000000010 -> 000000000000010
   000000000000100 -> 000000000000100
   000000000001000 -> 000000000001000
   000000000010000 -> 000000000010000
   000000000100000 -> 000000000100000
   000000001000000 -> 000000001000000
   000000010000000 -> 000000010000000
   000000100000000 -> 000000100000000
   000001000000000 -> 000001000000000
   000010000000000 -> 000010000000000
   000100000000000 -> 000100000000000
   001000000000000 -> 001000000000000
   010000000000000 -> 010000000000000
   100000000000000 -> 100000000000000
Encoding state machine work.nbnjbfrkqwq(qhrkzzskhwz)-tkcbxxqbtfx[0:17]
original code -> new code
   000000000000000001 -> 000000000000000001
   000000000000000010 -> 000000000000000010
   000000000000000100 -> 000000000000000100
   000000000000001000 -> 000000000000001000
   000000000000010000 -> 000000000000010000
   000000000000100000 -> 000000000000100000
   000000000001000000 -> 000000000001000000
   000000000010000000 -> 000000000010000000
   000000000100000000 -> 000000000100000000
   000000001000000000 -> 000000001000000000
   000000010000000000 -> 000000010000000000
   000000100000000000 -> 000000100000000000
   000001000000000000 -> 000001000000000000
   000010000000000000 -> 000010000000000000
   000100000000000000 -> 000100000000000000
   001000000000000000 -> 001000000000000000
   010000000000000000 -> 010000000000000000
   100000000000000000 -> 100000000000000000
@N:MF176 :  | Default generator successful  
@N:MF179 : smev.vhd(173) | Found 12 bit by 12 bit '<' comparator, 'pvtdpmmqdpp.un2_pbzxzjhqhwz'
@N:MF238 : smev.vhd(183) | Found 5 bit incrementor, 'un3_ckghxwbsztp[4:0]'
Encoding state machine work.cwgmnvwgkwq(wzrwkfmxjkf)-zwnnqcvfccb[0:14]
original code -> new code
   000000000000001 -> 000000000000001
   000000000000010 -> 000000000000010
   000000000000100 -> 000000000000100
   000000000001000 -> 000000000001000
   000000000010000 -> 000000000010000
   000000000100000 -> 000000000100000
   000000001000000 -> 000000001000000
   000000010000000 -> 000000010000000
   000000100000000 -> 000000100000000
   000001000000000 -> 000001000000000
   000010000000000 -> 000010000000000
   000100000000000 -> 000100000000000
   001000000000000 -> 001000000000000
   010000000000000 -> 010000000000000
   100000000000000 -> 100000000000000
Encoding state machine work.ccfdxrhchsz(djzfpsxghmt)-frcskdnwvmx[0:11]
original code -> new code
   000000000001 -> 000000000001
   000000000010 -> 000000000010
   000000000100 -> 000000000100
   000000001000 -> 000000001000
   000000010000 -> 000000010000
   000000100000 -> 000000100000
   000001000000 -> 000001000000
   000010000000 -> 000010000000
   000100000000 -> 000100000000
   001000000000 -> 001000000000
   010000000000 -> 010000000000
   100000000000 -> 100000000000
@W:MO129 : initcfg_xf.vhd(32) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.zmbsbbtjszd has been reduced to a combinational gate by constant propagation
@W:MO129 : initcfg_xf.vhd(32) | Sequential instance user_clk_sel.u_jhmkpjjmdkx.cjjcvbqtckq has been reduced to a combinational gate by constant propagation
Automatic dissolve during optimization of view:work.INITCFG(behavior) of u_grwzcnqmqzm(grwzcnqmqzm)
Automatic dissolve during optimization of view:work.nvm_init_init_wrapper(def_arch) of U0(INITCFG)
Automatic dissolve during optimization of view:work.nvm_init(def_arch) of nvm_init_init_wrapper_inst(nvm_init_init_wrapper)

Finished factoring (Time elapsed 0h:00m:08s; Memory used current: 35MB peak: 36MB)
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[31] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[30] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[29] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[28] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[27] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[26] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[25] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[24] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[23] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[22] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[21] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[20] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[19] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[18] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[17] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[16] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[15] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[14] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[4] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : smtr.vhd(123) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_smtr_wrapper_inst.U0.u_ccfdxrhchsz.mwzbqqvzwjt[1] of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : assc.vhd(170) | Removing sequential instance ADC_BLOCK.voltage_n50_50_33_15_assc_wrapper_inst.U0.u_cwgmnvwgkwq.rgqpfbkzbqs of view:PrimLib.dffr(prim) because there are no references to its outputs 
@W:BN116 : initcfg_xb.vhd(51) | Removing sequential instance NVM_BLK.nvm_init_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[8] of view:PrimLib.dffs(prim) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:08s; Memory used current: 35MB peak: 36MB)
@W:MO129 : initcfg_xb.vhd(42) | Sequential instance NVM_BLK.nvm_init_init_wrapper_inst.U0.u_grwzcnqmqzm.save_fsm.u_wbsfnwwctpn.crpwsdfhcqq[6] has been reduced to a combinational gate by constant propagation

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:09s; Memory used current: 35MB peak: 36MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:09s; Memory used current: 35MB peak: 37MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:10s; Memory used current: 35MB peak: 37MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:10s; Memory used current: 35MB peak: 37MB)

Finished preparing to map (Time elapsed 0h:00m:12s; Memory used current: 36MB peak: 37MB)
Promoting Net SYS_RESET_c on CLKBUF  SYS_RESET_pad
Promoting Net MAIN_CLK on CLKINT  I_149
Promoting Net INIT_DONE_OUTPUT_c on CLKINT  I_150
Promoting Net ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] on CLKINT  I_151
Replicating NVM_BLK.nvm_init_init_wrapper_inst.U0.u_grwzcnqmqzm.address_gen.u_dxwqxgdccxc.wqwwrvhjsjn_i[0], fanout 15 segments 2
Buffering SYS_CLK_20MHZ_c, fanout 27 segments 3
Replicating NVM_BLK.nvm_init_init_wrapper_inst.U0.u_grwzcnqmqzm.user_control.u_ffppvfwnggt.jsnhqgkgbcr.un1_wxqqqsndpvg, fanout 18 segments 2
Replicating NVM_BLK.nvm_init_init_wrapper_inst.U0.u_grwzcnqmqzm.bfcqzvtnrcn, fanout 14 segments 2
Replicating ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.tkcbxxqbtfx[4], fanout 30 segments 3
Replicating ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rgmpzqrbghh, fanout 18 segments 2
Replicating ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[2], fanout 43 segments 4
Replicating ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[1], fanout 41 segments 4
Replicating ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[0], fanout 38 segments 4
Replicating ADC_BLOCK.voltage_n50_50_33_15_assc_wrapper_inst.U0.u_cwgmnvwgkwq.zwnnqcvfccb[3], fanout 15 segments 2
Replicating ADC_BLOCK.voltage_n50_50_33_15_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[3], fanout 17 segments 2
Replicating ADC_BLOCK.voltage_n50_50_33_15_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[2], fanout 24 segments 2
Replicating ADC_BLOCK.voltage_n50_50_33_15_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[1], fanout 27 segments 3
Replicating ADC_BLOCK.voltage_n50_50_33_15_assc_wrapper_inst.U0.u_cwgmnvwgkwq.jrdxqdwndbg[0], fanout 25 segments 3
Buffering ADC_BLOCK.TR_RAM_DO_B_net_net_2, fanout 18 segments 2
Buffering ADC_BLOCK.TR_RAM_DO_B_net_net_4, fanout 15 segments 2
Buffering ADC_BLOCK.TR_RAM_DO_B_net_net_7, fanout 16 segments 2
Replicating ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bskrjhjvqpf_1_sqmuxa, fanout 15 segments 2
Replicating ADC_BLOCK.ADC_START_net, fanout 13 segments 2

Finished technology mapping (Time elapsed 0h:00m:13s; Memory used current: 37MB peak: 38MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:14s; Memory used current: 37MB peak: 38MB)

Added 5 Buffers
Added 24 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:14s; Memory used current: 37MB peak: 38MB)
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 
@N:BN191 :  | Writing property annotation file G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_rev2\synthesis\my_TOP.tap. 
Writing Analyst data base G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_rev2\synthesis\my_TOP.srm
@N:BN225 :  | Writing default property annotation file G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_rev2\synthesis\my_TOP.map. 
Writing EDIF Netlist and constraint files
Found clock my_TOP|SYS_CLK_20MHZ with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu May 18 12:33:58 2006
#


Top view:               my_TOP
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N:MT195 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT197 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: -28.973

                         Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock           Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------------
my_TOP|SYS_CLK_20MHZ     100.0 MHz     25.7 MHz      10.000        38.973        -28.973     inferred     Inferred_clkgroup_0
=============================================================================================================================





Clock Relationships
*******************

Clocks                                      |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------
Starting              Ending                |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------
my_TOP|SYS_CLK_20MHZ  my_TOP|SYS_CLK_20MHZ  |  10.000      -28.973  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: my_TOP|SYS_CLK_20MHZ
====================================



Starting Points with Worst Slack
********************************

                                                                                       Starting                                                           Arrival            
Instance                                                                               Reference                Type         Pin     Net                  Time        Slack  
                                                                                       Clock                                                                                 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]       my_TOP|SYS_CLK_20MHZ     DFN1E0C0     Q       rdgwgtpkbgc_0[3]     0.364       -28.973
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc_0[0]     my_TOP|SYS_CLK_20MHZ     DFN1E0C0     Q       rdgwgtpkbgc_0[0]     0.364       -27.054
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[5]       my_TOP|SYS_CLK_20MHZ     DFN1E1C0     Q       rqrqhcwpqdn[5]       0.364       -26.655
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[3]       my_TOP|SYS_CLK_20MHZ     DFN1E1C0     Q       rqrqhcwpqdn[3]       0.364       -26.551
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[1]       my_TOP|SYS_CLK_20MHZ     DFN1E1C0     Q       rqrqhcwpqdn[1]       0.364       -26.505
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[2]       my_TOP|SYS_CLK_20MHZ     DFN1E1C0     Q       rqrqhcwpqdn[2]       0.364       -26.247
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc_1[2]     my_TOP|SYS_CLK_20MHZ     DFN1E0C0     Q       rdgwgtpkbgc_1[2]     0.364       -26.124
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rqrqhcwpqdn[4]       my_TOP|SYS_CLK_20MHZ     DFN1E1C0     Q       rqrqhcwpqdn[4]       0.364       -26.093
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[8]       my_TOP|SYS_CLK_20MHZ     DFN1C0       Q       bnvtvdkcnpp[8]       0.364       -25.777
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[2]       my_TOP|SYS_CLK_20MHZ     DFN1C0       Q       bnvtvdkcnpp[2]       0.364       -25.777
=============================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                      Starting                                                                Required            
Instance                                                                              Reference                Type       Pin       Net                       Time         Slack  
                                                                                      Clock                                                                                       
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB1     EV_RAM_DI_B_net_net_6     8.930        -28.973
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB0     EV_RAM_DI_B_net_net_7     8.930        -27.791
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[10]     my_TOP|SYS_CLK_20MHZ     DFN1C0     D         bnvtvdkcnpp_9[10]         9.590        -26.915
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB4     EV_RAM_DI_B_net_net_3     8.930        -26.107
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB8     EV_RAM_DI_B_net[8]        8.930        -26.090
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB2     EV_RAM_DI_B_net_net_5     8.930        -25.894
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnvtvdkcnpp[9]      my_TOP|SYS_CLK_20MHZ     DFN1C0     D         bnvtvdkcnpp_9[9]          9.690        -25.645
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB6     EV_RAM_DI_B_net_net_1     8.930        -25.542
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB7     Z\\EV_RAM_DI_B_net\\      8.930        -25.035
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0       my_TOP|SYS_CLK_20MHZ     RAM4K9     DINB3     EV_RAM_DI_B_net_net_4     8.930        -24.937
==================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      37.903
    = Slack (critical) :                     -28.973

    Number of logic level(s):                19
    Starting point:                          ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] / Q
    Ending point:                            ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0 / DINB1
    The start point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLK
    The end   point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLKB

Instance / Net                                                                                                                Pin       Pin               Arrival     No. of    
Name                                                                                                             Type         Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 DFN1E0C0     Q         Out     0.364     0.364       -         
rdgwgtpkbgc_0[3]                                                                                                 Net          -         -       0.844     -           1         
I_151                                                                                                            CLKINT       A         In      -         1.208       -         
I_151                                                                                                            CLKINT       Y         Out     0.100     1.308       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 Net          -         -       7.472     -           72        
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d_s[2]                          OR2A         B         In      -         8.779       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d_s[2]                          OR2A         Y         Out     0.362     9.141       -         
bnwcvzjbgtc_11_d_s[2]                                                                                            Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d[2]                            MX2B         S         In      -         10.560      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d[2]                            MX2B         Y         Out     0.271     10.831      -         
bnwcvzjbgtc_11_d[2]                                                                                              Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          B         In      -         11.675      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          Y         Out     0.325     12.000      -         
bnwcvzjbgtc_12_d_0_d[2]                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         A         In      -         12.843      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         Y         Out     0.328     13.171      -         
bnwcvzjbgtc_12_d_0[2]                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          A         In      -         14.015      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          Y         Out     0.328     14.343      -         
bnwcvzjbgtc_12[2]                                                                                                Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_96                                           XOR3         C         In      -         16.325      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_96                                           XOR3         Y         Out     0.551     16.875      -         
N_252                                                                                                            Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I2_P0N        OR2          A         In      -         18.857      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I2_P0N        OR2          Y         Out     0.287     19.144      -         
ADD_18x18_medium_I2_P0N                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I33_Y         OR2B         A         In      -         19.988      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I33_Y         OR2B         Y         Out     0.293     20.281      -         
N299                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_un1_Y     OR2A         B         In      -         21.700      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_un1_Y     OR2A         Y         Out     0.362     22.062      -         
ADD_18x18_medium_I49_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_Y         OR2A         A         In      -         22.906      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_Y         OR2A         Y         Out     0.305     23.211      -         
N316                                                                                                             Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         A         In      -         25.755      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         Y         Out     0.293     26.048      -         
ADD_18x18_medium_I61_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         A         In      -         26.891      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         Y         Out     0.305     27.196      -         
N351                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        C         In      -         29.178      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        Y         Out     0.370     29.548      -         
ADD_18x18_medium_I67_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          C         In      -         30.392      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          Y         Out     0.416     30.808      -         
N343                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         B         In      -         32.227      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         Y         Out     0.327     32.554      -         
ADD_18x18_medium_I84_Y                                                                                           Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        B         In      -         33.397      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        Y         Out     0.520     33.917      -         
fqkdsnjfpdb_i[16]                                                                                                Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         B         In      -         35.337      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         Y         Out     0.362     35.699      -         
fqkdsnjfpdb_m[16]                                                                                                Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        A         In      -         36.542      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        Y         Out     0.517     37.059      -         
EV_RAM_DI_B_net_net_6                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0                                  RAM4K9       DINB1     In      -         37.903      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 38.973 is 8.055(20.7%) logic and 30.918(79.3%) route.


Path information for path number 2: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      37.802
    = Slack (non-critical) :                 -28.872

    Number of logic level(s):                18
    Starting point:                          ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] / Q
    Ending point:                            ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0 / DINB1
    The start point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLK
    The end   point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLKB

Instance / Net                                                                                                                Pin       Pin               Arrival     No. of    
Name                                                                                                             Type         Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 DFN1E0C0     Q         Out     0.364     0.364       -         
rdgwgtpkbgc_0[3]                                                                                                 Net          -         -       0.844     -           1         
I_151                                                                                                            CLKINT       A         In      -         1.208       -         
I_151                                                                                                            CLKINT       Y         Out     0.100     1.308       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 Net          -         -       7.472     -           72        
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_s[2]                            OR2A         A         In      -         8.779       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_s[2]                            OR2A         Y         Out     0.305     9.084       -         
bnwcvzjbgtc_12_s[2]                                                                                              Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          S         In      -         11.628      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          Y         Out     0.271     11.899      -         
bnwcvzjbgtc_12_d_0_d[2]                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         A         In      -         12.743      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         Y         Out     0.328     13.071      -         
bnwcvzjbgtc_12_d_0[2]                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          A         In      -         13.914      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          Y         Out     0.328     14.242      -         
bnwcvzjbgtc_12[2]                                                                                                Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_96                                           XOR3         C         In      -         16.224      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_96                                           XOR3         Y         Out     0.551     16.775      -         
N_252                                                                                                            Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I2_P0N        OR2          A         In      -         18.757      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I2_P0N        OR2          Y         Out     0.287     19.044      -         
ADD_18x18_medium_I2_P0N                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I33_Y         OR2B         A         In      -         19.887      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I33_Y         OR2B         Y         Out     0.293     20.180      -         
N299                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_un1_Y     OR2A         B         In      -         21.599      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_un1_Y     OR2A         Y         Out     0.362     21.961      -         
ADD_18x18_medium_I49_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_Y         OR2A         A         In      -         22.805      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I49_Y         OR2A         Y         Out     0.305     23.110      -         
N316                                                                                                             Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         A         In      -         25.654      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         Y         Out     0.293     25.947      -         
ADD_18x18_medium_I61_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         A         In      -         26.791      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         Y         Out     0.305     27.096      -         
N351                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        C         In      -         29.077      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        Y         Out     0.370     29.447      -         
ADD_18x18_medium_I67_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          C         In      -         30.291      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          Y         Out     0.416     30.707      -         
N343                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         B         In      -         32.126      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         Y         Out     0.327     32.453      -         
ADD_18x18_medium_I84_Y                                                                                           Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        B         In      -         33.297      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        Y         Out     0.520     33.817      -         
fqkdsnjfpdb_i[16]                                                                                                Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         B         In      -         35.236      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         Y         Out     0.362     35.598      -         
fqkdsnjfpdb_m[16]                                                                                                Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        A         In      -         36.441      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        Y         Out     0.517     36.959      -         
EV_RAM_DI_B_net_net_6                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0                                  RAM4K9       DINB1     In      -         37.802      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 38.872 is 7.673(19.7%) logic and 31.199(80.3%) route.


Path information for path number 3: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      37.593
    = Slack (non-critical) :                 -28.663

    Number of logic level(s):                18
    Starting point:                          ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] / Q
    Ending point:                            ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0 / DINB1
    The start point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLK
    The end   point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLKB

Instance / Net                                                                                                                Pin       Pin               Arrival     No. of    
Name                                                                                                             Type         Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 DFN1E0C0     Q         Out     0.364     0.364       -         
rdgwgtpkbgc_0[3]                                                                                                 Net          -         -       0.844     -           1         
I_151                                                                                                            CLKINT       A         In      -         1.208       -         
I_151                                                                                                            CLKINT       Y         Out     0.100     1.308       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 Net          -         -       7.472     -           72        
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d_s[2]                          OR2A         B         In      -         8.779       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d_s[2]                          OR2A         Y         Out     0.362     9.141       -         
bnwcvzjbgtc_11_d_s[2]                                                                                            Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d[2]                            MX2B         S         In      -         10.560      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d[2]                            MX2B         Y         Out     0.271     10.831      -         
bnwcvzjbgtc_11_d[2]                                                                                              Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          B         In      -         11.675      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          Y         Out     0.325     12.000      -         
bnwcvzjbgtc_12_d_0_d[2]                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         A         In      -         12.843      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         Y         Out     0.328     13.171      -         
bnwcvzjbgtc_12_d_0[2]                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          A         In      -         14.015      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          Y         Out     0.328     14.343      -         
bnwcvzjbgtc_12[2]                                                                                                Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_100_0                                        OA1          A         In      -         16.325      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_100_0                                        OA1          Y         Out     0.550     16.875      -         
G_100_0                                                                                                          Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I3_P0N        NOR3         C         In      -         19.419      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I3_P0N        NOR3         Y         Out     0.416     19.835      -         
N241                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I31_Y         NOR2         B         In      -         21.816      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I31_Y         NOR2         Y         Out     0.362     22.178      -         
N297                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I46_Y         NOR3C        C         In      -         23.598      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I46_Y         NOR3C        Y         Out     0.370     23.968      -         
N313                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         B         In      -         25.387      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         Y         Out     0.351     25.738      -         
ADD_18x18_medium_I61_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         A         In      -         26.581      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         Y         Out     0.305     26.887      -         
N351                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        C         In      -         28.868      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        Y         Out     0.370     29.238      -         
ADD_18x18_medium_I67_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          C         In      -         30.082      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          Y         Out     0.416     30.498      -         
N343                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         B         In      -         31.917      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         Y         Out     0.327     32.244      -         
ADD_18x18_medium_I84_Y                                                                                           Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        B         In      -         33.088      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        Y         Out     0.520     33.608      -         
fqkdsnjfpdb_i[16]                                                                                                Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         B         In      -         35.027      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         Y         Out     0.362     35.389      -         
fqkdsnjfpdb_m[16]                                                                                                Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        A         In      -         36.232      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        Y         Out     0.517     36.749      -         
EV_RAM_DI_B_net_net_6                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0                                  RAM4K9       DINB1     In      -         37.593      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 38.663 is 8.013(20.7%) logic and 30.650(79.3%) route.


Path information for path number 4: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      37.492
    = Slack (non-critical) :                 -28.562

    Number of logic level(s):                17
    Starting point:                          ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] / Q
    Ending point:                            ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0 / DINB1
    The start point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLK
    The end   point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLKB

Instance / Net                                                                                                                Pin       Pin               Arrival     No. of    
Name                                                                                                             Type         Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 DFN1E0C0     Q         Out     0.364     0.364       -         
rdgwgtpkbgc_0[3]                                                                                                 Net          -         -       0.844     -           1         
I_151                                                                                                            CLKINT       A         In      -         1.208       -         
I_151                                                                                                            CLKINT       Y         Out     0.100     1.308       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 Net          -         -       7.472     -           72        
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_s[2]                            OR2A         A         In      -         8.779       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_s[2]                            OR2A         Y         Out     0.305     9.084       -         
bnwcvzjbgtc_12_s[2]                                                                                              Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          S         In      -         11.628      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          Y         Out     0.271     11.899      -         
bnwcvzjbgtc_12_d_0_d[2]                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         A         In      -         12.743      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         Y         Out     0.328     13.071      -         
bnwcvzjbgtc_12_d_0[2]                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          A         In      -         13.914      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          Y         Out     0.328     14.242      -         
bnwcvzjbgtc_12[2]                                                                                                Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_100_0                                        OA1          A         In      -         16.224      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_100_0                                        OA1          Y         Out     0.550     16.774      -         
G_100_0                                                                                                          Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I3_P0N        NOR3         C         In      -         19.318      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I3_P0N        NOR3         Y         Out     0.416     19.734      -         
N241                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I31_Y         NOR2         B         In      -         21.716      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I31_Y         NOR2         Y         Out     0.362     22.078      -         
N297                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I46_Y         NOR3C        C         In      -         23.497      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I46_Y         NOR3C        Y         Out     0.370     23.867      -         
N313                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         B         In      -         25.286      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         Y         Out     0.351     25.637      -         
ADD_18x18_medium_I61_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         A         In      -         26.481      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         Y         Out     0.305     26.786      -         
N351                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        C         In      -         28.768      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        Y         Out     0.370     29.138      -         
ADD_18x18_medium_I67_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          C         In      -         29.981      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          Y         Out     0.416     30.397      -         
N343                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         B         In      -         31.817      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         Y         Out     0.327     32.143      -         
ADD_18x18_medium_I84_Y                                                                                           Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        B         In      -         32.987      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        Y         Out     0.520     33.507      -         
fqkdsnjfpdb_i[16]                                                                                                Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         B         In      -         34.926      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         Y         Out     0.362     35.288      -         
fqkdsnjfpdb_m[16]                                                                                                Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        A         In      -         36.132      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        Y         Out     0.517     36.649      -         
EV_RAM_DI_B_net_net_6                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0                                  RAM4K9       DINB1     In      -         37.492      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 38.562 is 7.631(19.8%) logic and 30.931(80.2%) route.


Path information for path number 5: 
    Requested Period:                        10.000
    - Setup time:                            1.070
    = Required time:                         8.930

    - Propagation time:                      37.380
    = Slack (non-critical) :                 -28.450

    Number of logic level(s):                18
    Starting point:                          ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3] / Q
    Ending point:                            ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0 / DINB1
    The start point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLK
    The end   point is clocked by            my_TOP|SYS_CLK_20MHZ [rising] on pin CLKB

Instance / Net                                                                                                                Pin       Pin               Arrival     No. of    
Name                                                                                                             Type         Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 DFN1E0C0     Q         Out     0.364     0.364       -         
rdgwgtpkbgc_0[3]                                                                                                 Net          -         -       0.844     -           1         
I_151                                                                                                            CLKINT       A         In      -         1.208       -         
I_151                                                                                                            CLKINT       Y         Out     0.100     1.308       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.rdgwgtpkbgc[3]                                 Net          -         -       7.472     -           72        
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d_s[2]                          OR2A         B         In      -         8.779       -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d_s[2]                          OR2A         Y         Out     0.362     9.141       -         
bnwcvzjbgtc_11_d_s[2]                                                                                            Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d[2]                            MX2B         S         In      -         10.560      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_11_d[2]                            MX2B         Y         Out     0.271     10.831      -         
bnwcvzjbgtc_11_d[2]                                                                                              Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          B         In      -         11.675      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0_d[2]                        MX2          Y         Out     0.325     12.000      -         
bnwcvzjbgtc_12_d_0_d[2]                                                                                          Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         A         In      -         12.843      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12_d_0[2]                          MX2C         Y         Out     0.328     13.171      -         
bnwcvzjbgtc_12_d_0[2]                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          A         In      -         14.015      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.bnwcvzjbgtc_12[2]                              MX2          Y         Out     0.328     14.343      -         
bnwcvzjbgtc_12[2]                                                                                                Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_98                                           NOR2B        B         In      -         16.325      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.G_98                                           NOR2B        Y         Out     0.351     16.676      -         
N_255                                                                                                            Net          -         -       2.544     -           4         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I3_P0N        NOR3         B         In      -         19.220      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I3_P0N        NOR3         Y         Out     0.402     19.622      -         
N241                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I31_Y         NOR2         B         In      -         21.603      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I31_Y         NOR2         Y         Out     0.362     21.965      -         
N297                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I46_Y         NOR3C        C         In      -         23.385      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I46_Y         NOR3C        Y         Out     0.370     23.755      -         
N313                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         B         In      -         25.174      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_un1_Y     OR2B         Y         Out     0.351     25.525      -         
ADD_18x18_medium_I61_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         A         In      -         26.369      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I61_Y         OR2A         Y         Out     0.305     26.674      -         
N351                                                                                                             Net          -         -       1.982     -           3         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        C         In      -         28.655      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_un1_Y     NOR3C        Y         Out     0.370     29.025      -         
ADD_18x18_medium_I67_un1_Y                                                                                       Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          C         In      -         29.869      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I67_Y         OR3          Y         Out     0.416     30.285      -         
N343                                                                                                             Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         B         In      -         31.704      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I84_Y         AO1A         Y         Out     0.327     32.031      -         
ADD_18x18_medium_I84_Y                                                                                           Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        B         In      -         32.875      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_0_0.ADD_18x18_medium_I108_Y        XNOR2        Y         Out     0.520     33.395      -         
fqkdsnjfpdb_i[16]                                                                                                Net          -         -       1.419     -           2         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         B         In      -         34.814      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.fqkdsnjfpdb_m[16]                              OR2A         Y         Out     0.362     35.176      -         
fqkdsnjfpdb_m[16]                                                                                                Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        A         In      -         36.019      -         
ADC_BLOCK.voltage_n50_50_33_15_smev_wrapper_inst.U0.u_nbnjbfrkqwq.zbqggxmnpbs_r[1]                               AOI1B        Y         Out     0.517     36.536      -         
EV_RAM_DI_B_net_net_6                                                                                            Net          -         -       0.844     -           1         
ADC_BLOCK.voltage_n50_50_33_15_smev_ram_inst.voltage_n50_50_33_15_smev_ram_R0C0                                  RAM4K9       DINB1     In      -         37.380      -         
================================================================================================================================================================================
Total path delay (propagation time + setup) of 38.450 is 7.800(20.3%) logic and 30.650(79.7%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell my_TOP.def_arch
  Cell usage:
              cell count     area count*area
               MX2   262      1.0      262.0
            DFN1C0   152      1.0      152.0
             NOR2A   122      1.0      122.0
          DFN1E1C0   107      1.0      107.0
             NOR2B    98      1.0       98.0
              OR2B    84      1.0       84.0
              OR2A    60      1.0       60.0
              XOR2    57      1.0       57.0
             AOI1B    53      1.0       53.0
              MX2C    39      1.0       39.0
              OR3C    37      1.0       37.0
               OR2    35      1.0       35.0
              OR3B    33      1.0       33.0
               VCC    31      0.0        0.0
               GND    31      0.0        0.0
             NOR3C    29      1.0       29.0
              NOR2    29      1.0       29.0
          DFN1E0C0    27      1.0       27.0
              AO1B    26      1.0       26.0
              AO1C    25      1.0       25.0
             XNOR2    24      1.0       24.0
              AND2    24      1.0       24.0
               OR3    23      1.0       23.0
             NOR3A    19      1.0       19.0
             NOR3B    18      1.0       18.0
               AO1    17      1.0       17.0
              OA1A    17      1.0       17.0
               OA1    17      1.0       17.0
              OR3A    16      1.0       16.0
             XNOR3    16      1.0       16.0
              NOR3    16      1.0       16.0
              AO1D    12      1.0       12.0
              OAI1    11      1.0       11.0
              OA1C    11      1.0       11.0
              OA1B    11      1.0       11.0
           INBUF_A    10      0.0        0.0
              MX2B     8      1.0        8.0
            OUTBUF     8      0.0        0.0
            DFN1P0     7      1.0        7.0
              AX1D     7      1.0        7.0
              AO1A     7      1.0        7.0
              XA1A     7      1.0        7.0
              MX2A     6      1.0        6.0
              MAJ3     6      1.0        6.0
             AOI1A     5      1.0        5.0
              AO13     5      1.0        5.0
              BUFF     5      1.0        5.0
              AOI1     4      1.0        4.0
          OUTBUF_A     4      0.0        0.0
             INBUF     4      0.0        0.0
              AND3     4      1.0        4.0
            CLKINT     3      0.0        0.0
            RAM4K9     3      0.0        0.0
              XOR3     3      1.0        3.0
              AO18     3      1.0        3.0
             AND2A     3      1.0        3.0
               XA1     3      1.0        3.0
              AX1C     3      1.0        3.0
               AX1     2      1.0        2.0
               INV     2      1.0        2.0
            DFN1E1     2      1.0        2.0
              AX1B     2      1.0        2.0
             AXOI5     1      1.0        1.0
                AB     1      0.0        0.0
              XO1A     1      1.0        1.0
             NAND2     1      1.0        1.0
            CLKBUF     1      0.0        0.0
              XA1B     1      1.0        1.0
             AXOI7     1      1.0        1.0
               NVM     1      0.0        0.0
              ZOR3     1      1.0        1.0
              AX1E     1      1.0        1.0
             XAI1A     1      1.0        1.0
                   -----          ----------
             TOTAL  1726              1629.0
Mapper successful!
Process took 0h:00m:19s realtime, 0h:00m:15s cputime
# Thu May 18 12:33:58 2006

###########################################################]