#Build: Synplify Pro 8.5B, Build 429R, Dec  8 2005
#install: D:\Libero71\Synplify\Synplify_85B
#OS: Windows XP 5.1
#Hostname: WXP-ALIM

#Wed May 03 18:10:21 2006

$ Start of Compile
#Wed May 03 18:10:21 2006

Synplicity VHDL Compiler, version 3.4.1, Build 089R, built Mar  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@N: : voltage_seq_control.vhd(5) | Top entity is set to voltage_seq_control.
VHDL syntax check successful!
Options changed - recompiling
@N:CD630 : voltage_seq_control.vhd(5) | Synthesizing work.voltage_seq_control.def_arch 
@N:CD231 : voltage_seq_control.vhd(42) | Using onehot encoding for type state_type (warmup="10000000000000")
Post processing for work.voltage_seq_control.def_arch
@W:CL112 : voltage_seq_control.vhd(61) | Feedback mux created for signal all_supply_on. Did you forget the set/reset assignment for this signal?
@W:CL112 : voltage_seq_control.vhd(61) | Feedback mux created for signal all_load_on. Did you forget the set/reset assignment for this signal?
@N:CL201 : voltage_seq_control.vhd(61) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 14 reachable states with original encodings of:
   00000000000001
   00000000000010
   00000000000100
   00000000001000
   00000000010000
   00000000100000
   00000001000000
   00000010000000
   00000100000000
   00001000000000
   00010000000000
   00100000000000
   01000000000000
   10000000000000
@W:CL159 : voltage_seq_control.vhd(18) | Input acn5p0v_over1p5a is unused
@W:CL159 : voltage_seq_control.vhd(23) | Input ac5p0v_ac5p0v_over2p0a is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 03 18:10:21 2006

###########################################################[
Synplicity Proasic Technology Mapper, Version 8.4.0.p, Build 075R, Built Mar  8 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Version 8.5B
@W:BN227 :  | This data was produced by a restricted version of Synplicity software. The results contain Synplicity IP and are not licensed to be used for production design work or design services 
@N:MF249 :  | Running in 32-bit mode. 
@N: :  | Gated clock conversion disabled  
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 26MB peak: 27MB)
Encoding state machine work.voltage_seq_control(def_arch)-state[0:13]
original code -> new code
   00000000000001 -> 00000000000001
   00000000000010 -> 00000000000010
   00000000000100 -> 00000000000100
   00000000001000 -> 00000000001000
   00000000010000 -> 00000000010000
   00000000100000 -> 00000000100000
   00000001000000 -> 00000001000000
   00000010000000 -> 00000010000000
   00000100000000 -> 00000100000000
   00001000000000 -> 00001000000000
   00010000000000 -> 00010000000000
   00100000000000 -> 00100000000000
   01000000000000 -> 01000000000000
   10000000000000 -> 10000000000000

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 27MB peak: 28MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)
Buffering SYS_RESET_c, fanout 20 segments 2
Buffering SYS_CLK_c, fanout 20 segments 2

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)

Added 2 Buffers
Added 0 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 27MB peak: 28MB)
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W:BN153 :  | View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W:BN154 :  | View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 
@N:BN191 :  | Writing property annotation file G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_prj\synthesis\voltage_seq_control.tap. 
Writing Analyst data base G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_prj\synthesis\voltage_seq_control.srm
@N:BN225 :  | Writing default property annotation file G:\Appsnotes\Voltage_Sequencing_SGIP\Voltage_seq_prj\synthesis\voltage_seq_control.map. 
Writing EDIF Netlist and constraint files
Found clock voltage_seq_control|SYS_CLK with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed May 03 18:10:24 2006
#


Top view:               voltage_seq_control
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N:MT195 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT197 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: 4.940

                                Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                  Frequency     Frequency     Period        Period        Slack     Type         Group              
----------------------------------------------------------------------------------------------------------------------------------
voltage_seq_control|SYS_CLK     100.0 MHz     197.6 MHz     10.000        5.060         4.940     inferred     Inferred_clkgroup_0
==================================================================================================================================





Clock Relationships
*******************

Clocks                                                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------
voltage_seq_control|SYS_CLK  voltage_seq_control|SYS_CLK  |  10.000      4.940  |  No paths    -      |  No paths    -      |  No paths    -    
================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: voltage_seq_control|SYS_CLK
====================================



Starting Points with Worst Slack
********************************

              Starting                                                         Arrival          
Instance      Reference                       Type       Pin     Net           Time        Slack
              Clock                                                                             
------------------------------------------------------------------------------------------------
state[13]     voltage_seq_control|SYS_CLK     DFN1P1     Q       state[13]     0.364       4.940
state[5]      voltage_seq_control|SYS_CLK     DFN1C1     Q       state[5]      0.364       5.398
state[7]      voltage_seq_control|SYS_CLK     DFN1C1     Q       state[7]      0.364       5.398
state[3]      voltage_seq_control|SYS_CLK     DFN1C1     Q       state[3]      0.364       5.807
state[0]      voltage_seq_control|SYS_CLK     DFN1C1     Q       state[0]      0.364       5.818
state[1]      voltage_seq_control|SYS_CLK     DFN1C1     Q       state[1]      0.364       5.830
state[2]      voltage_seq_control|SYS_CLK     DFN1C1     Q       state[2]      0.364       5.830
state[12]     voltage_seq_control|SYS_CLK     DFN1C1     Q       state[12]     0.364       6.227
state[10]     voltage_seq_control|SYS_CLK     DFN1C1     Q       state[10]     0.364       6.238
state[11]     voltage_seq_control|SYS_CLK     DFN1C1     Q       state[11]     0.364       6.238
================================================================================================


Ending Points with Worst Slack
******************************

                   Starting                                                                       Required          
Instance           Reference                       Type         Pin     Net                       Time         Slack
                   Clock                                                                                            
--------------------------------------------------------------------------------------------------------------------
AV1p5v_ENABLE      voltage_seq_control|SYS_CLK     DFN1E0C1     E       un1_state_4_i_a3_0_a2     9.670        4.940
AV3p3v_ENABLE      voltage_seq_control|SYS_CLK     DFN1E0C1     E       un1_state_2_i_a3_0_a2     9.670        4.940
AV5p0v_ENABLE      voltage_seq_control|SYS_CLK     DFN1E0C1     E       un1_state_3_i_a3_0_a2     9.670        4.940
AVn5p0v_ENABLE     voltage_seq_control|SYS_CLK     DFN1E0C1     E       un1_state_1_i_a3_0_a2     9.670        4.940
state[12]          voltage_seq_control|SYS_CLK     DFN1C1       D       state_ns_i[1]             9.590        5.052
state[13]          voltage_seq_control|SYS_CLK     DFN1P1       D       state_ns[0]               9.590        5.052
all_load_on        voltage_seq_control|SYS_CLK     DFN1E0       D       un1_state_5_0             9.590        5.077
all_supply_on      voltage_seq_control|SYS_CLK     DFN1E0       D       un1_state_6_0             9.590        5.077
state[5]           voltage_seq_control|SYS_CLK     DFN1C1       D       state_ns[8]               9.590        5.398
state[7]           voltage_seq_control|SYS_CLK     DFN1C1       D       state_ns[6]               9.590        5.398
====================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            0.330
    = Required time:                         9.670

    - Propagation time:                      4.730
    = Slack (critical) :                     4.940

    Number of logic level(s):                1
    Starting point:                          state[13] / Q
    Ending point:                            AVn5p0v_ENABLE / E
    The start point is clocked by            voltage_seq_control|SYS_CLK [rising] on pin CLK
    The end   point is clocked by            voltage_seq_control|SYS_CLK [rising] on pin CLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                      Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
state[13]                 DFN1P1       Q        Out     0.364     0.364       -         
state[13]                 Net          -        -       3.320     -           8         
un1_state_1_i_a3_0_a2     NOR3         C        In      -         3.684       -         
un1_state_1_i_a3_0_a2     NOR3         Y        Out     0.416     4.100       -         
un1_state_1_i_a3_0_a2     Net          -        -       0.630     -           1         
AVn5p0v_ENABLE            DFN1E0C1     E        In      -         4.730       -         
========================================================================================
Total path delay (propagation time + setup) of 5.060 is 1.110(21.9%) logic and 3.950(78.1%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell voltage_seq_control.def_arch
  Cell usage:
              cell count     area count*area
             INBUF    15      0.0        0.0
            DFN1C1    13      1.0       13.0
            OUTBUF     6      0.0        0.0
              AO1C     5      1.0        5.0
              AO1B     5      1.0        5.0
              OR2A     5      1.0        5.0
              OR2B     5      1.0        5.0
          DFN1E0C1     4      1.0        4.0
              NOR3     4      1.0        4.0
              AO1A     3      1.0        3.0
            DFN1E0     2      1.0        2.0
             NOR2B     2      1.0        2.0
              BUFF     2      1.0        2.0
             NOR2A     1      1.0        1.0
            DFN1P1     1      1.0        1.0
               MX2     1      1.0        1.0
              MX2B     1      1.0        1.0
               VCC     1      0.0        0.0
               GND     1      0.0        0.0
                   -----          ----------
             TOTAL    77                54.0
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 03 18:10:24 2006

###########################################################]