#Build: Synplify Pro 8.8A1, Build 015R, Apr 16 2007 #install: C:\Libero\Libero80\Synplify\Synplify_88A1 #OS: Windows XP 5.1 #Hostname: WXP-ALIMS #Implementation: synthesis #Mon Jul 23 14:06:17 2007 $ Start of Compile #Mon Jul 23 14:06:17 2007 Synplicity VHDL Compiler, version 3.7.5, Build 159R, built Apr 13 2007 Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : Top_Level.vhd(22) | Top entity is set to Top_Level. VHDL syntax check successful! Options changed - recompiling @N:CD630 : Top_Level.vhd(22) | Synthesizing work.top_level.rtl @N:CD630 : AX_EDAC_SRAM256X8_EFLAGS_top.vhd(4) | Synthesizing work.ax_edac_sram256x8_eflags_top.behavioral @N:CD630 : edaci_18.vhd(23) | Synthesizing work.edaci.syn_def_arch @W:CD275 : axcelerator.vhd(2873) | Component declarations with different initial values are not supported. Port y of component gnd may have been given a different initial value in two different component declarations @W:CD275 : axcelerator.vhd(5362) | Component declarations with different initial values are not supported. Port y of component vcc may have been given a different initial value in two different component declarations @N:CD630 : axcelerator.vhd(4187) | Synthesizing axcelerator.or4a.syn_black_box Post processing for axcelerator.or4a.syn_black_box @N:CD630 : axcelerator.vhd(5362) | Synthesizing axcelerator.vcc.syn_black_box Post processing for axcelerator.vcc.syn_black_box @N:CD630 : axcelerator.vhd(1300) | Synthesizing axcelerator.cm8.syn_black_box Post processing for axcelerator.cm8.syn_black_box @N:CD630 : axcelerator.vhd(2873) | Synthesizing axcelerator.gnd.syn_black_box Post processing for axcelerator.gnd.syn_black_box @N:CD630 : axcelerator.vhd(1333) | Synthesizing axcelerator.cm8inv.syn_black_box Post processing for axcelerator.cm8inv.syn_black_box @N:CD630 : axcelerator.vhd(1698) | Synthesizing axcelerator.dfc1b.syn_black_box Post processing for axcelerator.dfc1b.syn_black_box @N:CD630 : axcelerator.vhd(68) | Synthesizing axcelerator.and2a.syn_black_box Post processing for axcelerator.and2a.syn_black_box @N:CD630 : axcelerator.vhd(132) | Synthesizing axcelerator.and4b.syn_black_box Post processing for axcelerator.and4b.syn_black_box @N:CD630 : axcelerator.vhd(4154) | Synthesizing axcelerator.or3a.syn_black_box Post processing for axcelerator.or3a.syn_black_box @N:CD630 : axcelerator.vhd(1762) | Synthesizing axcelerator.dfe3c.syn_black_box Post processing for axcelerator.dfe3c.syn_black_box @N:CD630 : axcelerator.vhd(61) | Synthesizing axcelerator.and2.syn_black_box Post processing for axcelerator.and2.syn_black_box @N:CD630 : axcelerator.vhd(5367) | Synthesizing axcelerator.xa1.syn_black_box Post processing for axcelerator.xa1.syn_black_box @N:CD630 : axcelerator.vhd(4125) | Synthesizing axcelerator.or2.syn_black_box Post processing for axcelerator.or2.syn_black_box @N:CD630 : axcelerator.vhd(2013) | Synthesizing axcelerator.dfp1b.syn_black_box Post processing for axcelerator.dfp1b.syn_black_box @N:CD630 : axcelerator.vhd(1148) | Synthesizing axcelerator.buff.syn_black_box Post processing for axcelerator.buff.syn_black_box @N:CD630 : axcelerator.vhd(5455) | Synthesizing axcelerator.xor2.syn_black_box Post processing for axcelerator.xor2.syn_black_box @N:CD630 : axcelerator.vhd(4162) | Synthesizing axcelerator.or3b.syn_black_box Post processing for axcelerator.or3b.syn_black_box @N:CD630 : axcelerator.vhd(123) | Synthesizing axcelerator.and4a.syn_black_box Post processing for axcelerator.and4a.syn_black_box @N:CD630 : axcelerator.vhd(82) | Synthesizing axcelerator.and3.syn_black_box Post processing for axcelerator.and3.syn_black_box @N:CD630 : axcelerator.vhd(4178) | Synthesizing axcelerator.or4.syn_black_box Post processing for axcelerator.or4.syn_black_box @N:CD630 : axcelerator.vhd(75) | Synthesizing axcelerator.and2b.syn_black_box Post processing for axcelerator.and2b.syn_black_box @N:CD630 : axcelerator.vhd(114) | Synthesizing axcelerator.and4.syn_black_box Post processing for axcelerator.and4.syn_black_box @N:CD630 : axcelerator.vhd(106) | Synthesizing axcelerator.and3c.syn_black_box Post processing for axcelerator.and3c.syn_black_box @N:CD630 : axcelerator.vhd(5415) | Synthesizing axcelerator.xnor2.syn_black_box Post processing for axcelerator.xnor2.syn_black_box @N:CD630 : axcelerator.vhd(4196) | Synthesizing axcelerator.or4b.syn_black_box Post processing for axcelerator.or4b.syn_black_box @N:CD630 : axcelerator.vhd(90) | Synthesizing axcelerator.and3a.syn_black_box Post processing for axcelerator.and3a.syn_black_box @N:CD630 : axcelerator.vhd(4132) | Synthesizing axcelerator.or2a.syn_black_box Post processing for axcelerator.or2a.syn_black_box @N:CD630 : axcelerator.vhd(3783) | Synthesizing axcelerator.nand4.syn_black_box Post processing for axcelerator.nand4.syn_black_box @N:CD630 : axcelerator.vhd(98) | Synthesizing axcelerator.and3b.syn_black_box Post processing for axcelerator.and3b.syn_black_box @N:CD630 : axcelerator.vhd(1714) | Synthesizing axcelerator.dfc1d.syn_black_box Post processing for axcelerator.dfc1d.syn_black_box @N:CD630 : axcelerator.vhd(4139) | Synthesizing axcelerator.or2b.syn_black_box Post processing for axcelerator.or2b.syn_black_box Post processing for work.edaci.syn_def_arch @N:CD630 : AX_EDAC_SRAM256X8_EFLAGS.vhd(7) | Synthesizing work.ax_edac_sram256x8_eflags.def_arch @W:CD275 : AX_EDAC_SRAM256X8_EFLAGS.vhd(37) | Component declarations with different initial values are not supported. Port y of component vcc may have been given a different initial value in two different component declarations @W:CD275 : AX_EDAC_SRAM256X8_EFLAGS.vhd(41) | Component declarations with different initial values are not supported. Port y of component gnd may have been given a different initial value in two different component declarations @N:CD630 : axcelerator.vhd(4724) | Synthesizing axcelerator.ram64k36.syn_black_box Post processing for axcelerator.ram64k36.syn_black_box Post processing for work.ax_edac_sram256x8_eflags.def_arch Post processing for work.ax_edac_sram256x8_eflags_top.behavioral Post processing for work.top_level.rtl @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Jul 23 14:06:18 2007 ###########################################################] Synplicity Proasic Technology Mapper, Version 8.8.0, Build 015R, Built Apr 15 2007 16:31:14 Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved Product Version Version 8.8A1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled Automatic dissolve during optimization of view:work.AX_EDAC_SRAM256X8_EFLAGS_top(behavioral) of uaxram(AX_EDAC_SRAM256X8_EFLAGS) Automatic dissolve at startup in view:work.AX_EDAC_SRAM256X8_EFLAGS_top(behavioral) of uedaci(edaci) Automatic dissolve at startup in view:work.Top_Level(rtl) of TestRAM(AX_EDAC_SRAM256X8_EFLAGS_top) RTL optimization done. Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 42MB peak: 44MB) Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 42MB peak: 44MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 42MB peak: 44MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 44MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 44MB) Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 44MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 44MB) Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 44MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------------- TestRAM.uaxram.RAMBLOCK_0_inst / RD12 12 TestRAM.uaxram.RAMBLOCK_0_inst / RD16 14 TestRAM.uedaci.XXDXXXXXXXXXXXXXXXXXF / y 11 RSTn_pad / y 114 : 32 asynchronous set/reset WE_pad / y 25 ============================================================================ Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 42MB peak: 44MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 42MB peak: 44MB) High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes ---------------------------------------------------------------------------- TestRAM.uaxram.RAMBLOCK_0_inst / RD12 12 TestRAM.uaxram.RAMBLOCK_0_inst / RD16 14 TestRAM.uedaci.XXDXXXXXXXXXXXXXXXXXF / y 11 RSTn_pad / y 114 : 32 asynchronous set/reset WE_pad / y 25 ============================================================================ Buffering WE_c, fanout 25 segments 3 Added 2 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 44MB) Writing Analyst data base D:\Appsnotes\2007\EDAC_SRAM_SEU_SIM\EDAC_Libero\EDAC_SRAM_SEU_SIM\synthesis\Top_Level.srm Writing EDIF Netlist and constraint files ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Jul 23 14:06:19 2007 # Top view: Top_Level Library name: adlib Operating conditions: milwc-1 ( T = 125.0, V = 1.42, P = 1.31, tree_type = worst_case ) Requested Frequency: 25.0 MHz Wire load mode: top Wire load model: ax125 Paths requested: 5 Constraint File(s): @N:MT195 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT197 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: 17.579 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------- Top_Level|CLK 25.0 MHz 206.6 MHz 40.000 4.841 17.579 inferred Inferred_clkgroup_0 ====================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------- Top_Level|CLK Top_Level|CLK | 40.000 24.174 | No paths - | 20.000 17.579 | No paths - ====================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Top_Level|CLK ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQ Top_Level|CLK dfe3c q XXDXXXXXXXXXXWXXXXXXXQZX 1.089 17.579 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXP Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXL 1.089 24.174 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXJH Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXXFD 1.089 24.246 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXL Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXF 1.089 25.121 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXHD Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXXJD 1.089 25.121 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXKH Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXXFK 1.089 25.121 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXV Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXJ 1.089 25.264 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXHK Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXX 1.089 25.264 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXHV Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXXM 1.089 25.264 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXL Top_Level|CLK dfe3c q XXDXXXXXXXXXXXXMXXXXXZXZXXXFP 1.089 25.264 ====================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------- TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQXX Top_Level|CLK dfc1d d XXDXXXXXXXXXXWXXXXXXXQXXZXZXX 19.877 17.579 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXFH Top_Level|CLK dfe3c d XXDXXXXXXXXXXXXMXXXXXXLZXZXXFK 39.877 24.174 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXJK Top_Level|CLK dfe3c d XXDXXXXXXXXXXXXMXXXXXXLZXZXXJF 39.877 25.236 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXV Top_Level|CLK dfe3c d XXDXXXXXXXXXXXXMXXXXXXLZXZXXJ 39.877 25.252 TestRAM.uedaci.XXDXXXXXXXXXXXXXXXXXHXXXXXXXZXZXX Top_Level|CLK dfc1b d XXDXXXXXXXXXXXXXXXXXHXYXXXF 39.877 25.396 TestRAM.uedaci.XXDXXXXXXXXXXXXXXXXXHXXXXXXXZXZXXF Top_Level|CLK dfc1b d XXDXXXXXXXXXXXXXXXXXHXYXXX 39.877 25.396 TestRAM.uedaci.XXDXXXXXXXXXXXXXXXXDXXXZX Top_Level|CLK dfe3c e XXDXXXXXXXXXXYXXXFF 39.877 25.791 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXHJ Top_Level|CLK dfe3c d XXDXXXXXXXXXXXXMXXXXXXLZXZXXFP 39.877 26.314 TestRAM.uedaci.XXDXXXXXXXXXXXXMXXXXXXXXJQ Top_Level|CLK dfe3c d XXDXXXXXXXXXXXXMXXXXXXLZXZXXHP 39.877 26.374 TestRAM.uedaci.XXDXXXXXXXXXXXWDXXXXX Top_Level|CLK dfe3c e XXDXXXXXXXXXXXXXXXXXPXXXXXXXXZXZXX 39.877 26.458 ==================================================================================================================================================== Worst Path Information View Worst Path in Analyst (RTL View) View Worst Path in Analyst (Tech View) *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.123 = Required time: 19.877 - Propagation time: 2.298 = Slack (critical) : 17.579 Number of logic level(s): 1 Starting point: TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQ / q Ending point: TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQXX / d The start point is clocked by Top_Level|CLK [rising] on pin clk The end point is clocked by Top_Level|CLK [falling] on pin clk Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQ dfe3c q Out 1.089 1.089 - XXDXXXXXXXXXXWXXXXXXXQZX Net - - 0.146 - 1 TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQXXXX and2a b In - 1.235 - TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQXXXX and2a y Out 0.916 2.152 - XXDXXXXXXXXXXWXXXXXXXQXXZXZXX Net - - 0.146 - 1 TestRAM.uedaci.XXDXXXXXXXXXXWXXXXXXXQXX dfc1d d In - 2.298 - ========================================================================================================= Total path delay (propagation time + setup) of 2.421 is 2.129(87.9%) logic and 0.292(12.1%) route. ##### END OF TIMING REPORT #####] --------------------------------------- Synthesized design as a chip Resource Usage Report of Top_Level Target Part: rtax250s-s Combinational Cells: 327 of 2816 (12%) Sequential Cells: 117 of 1408 (8%) Total Cells: 444 of 4224 (11%) Clock Buffers: 2 IO Cells: 51 Details: and2: 8 comb:1 and2a: 24 comb:1 and2b: 7 comb:1 and3: 2 comb:1 and3a: 2 comb:1 and3b: 19 comb:1 and3c: 1 comb:1 and4: 3 comb:1 and4a: 5 comb:1 and4b: 2 comb:1 and4c: 8 comb:1 buff: 18 comb:1 cm8: 168 comb:1 cm8inv: 117 dfp1b: 1 seq:1 nand4: 1 comb:2 or2: 11 comb:1 or2a: 3 comb:1 or2b: 1 comb:1 or3a: 3 comb:1 or3b: 2 comb:1 or4: 3 comb:1 or4a: 2 comb:1 or4b: 2 comb:1 xa1: 10 comb:1 xnor2: 2 comb:1 xor2: 19 comb:1 dfc1b: 37 seq:1 dfc1d: 1 seq:1 dfe3c: 78 seq:1 clkbuf: 2 clock buffer inbuf: 27 outbuf: 22 RAM64K36: 1 false: 4 true: 4 RAM/ROM Usage Summary Block Rams : 1 of 12 (8%) Mapper successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Jul 23 14:06:19 2007 ###########################################################]