SynaptiCAD
Overview
SynaptiCAD develops EDA tools that help engineers think critically about their designs and offers a complete line of VHDL and Verilog model generation, simulation, and timing diagram visualization tools. Microsemi's Libero Integrated Design Environment (IDE) can call SynaptiCAD's WaveFormer Pro or TestBencher Pro to provide a verification environment to generate testbenches for Libero IDE projects. WaveFormer Pro generates testbenches from a single timing diagram, and also adds Analog Signal Display and Interactive simulation for creating the timing diagrams. TestBencher Pro supports multi-diagram testbench and reactive model generation. SynaptiCAD also offers VeriLogger Extreme, a fast compiled Verilog simulator.
Products and Services
WaveFormer Pro is a revolutionary new rapid-prototyping EDA tool that helps you design faster and with fewer mistakes. Upgrade WaveFormer Lite to WaveFormer Pro and get analog signal display and digital timing analysis feature that enables you to automatically determine critical paths, verify timing margins, adjust for common delay effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing and perform RTL level simulation without the need for schematics or simulation models. When your timing diagram is complete, you can then generate digital stimuli for your favorite Verilog, VHDL, SPICE or gate-level simulator. WaveFormer Pro has the ability to import and annotate simulation and logic analyzer data for publication-quality design documentation. Download WaveFormer Pro from www.syncad.com
SynaptiCAD also offers, WaveFormer Lite, an entry-level version of WaveFormer Pro that was specifically designed to work with Libero IDE. This product can generate a testbench for Libero IDE from drawn timing diagrams but it cannot perform timing analysis or generate waveforms from Boolean equations. Contact SynaptiCAD directly at sales@syncad.com for information on this special product.
TestBencher Pro provides designers with a graphical environment for rapidly generating and testing bus-functional models for VHDL, Verilog, and SystemC. Whereas WaveFormer Pro generates testbenches using one timing diagram, TestBencher allows multiple timing diagrams to be linked together to generate bus functional models. Each timing diagram is a reusable bus transaction and they can be applied to the model under test using both specified and random data generation. TestBencher Pro dramatically reduces the time necessary to develop test suites by generating model code from language independent graphical timing diagrams and automating the build process.
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors. VeriLogger Extreme also comes with BugHunter Pro, a graphical Verilog/VHDL integrated development environment, which supports debugging with all major HDL simulators. BugHunter supports source-level debugging, a waveform compression engine for high-speed waveform dumping and viewing, and graphical testbench generation features for rapidly testing HDL models.
For information about pricing and obtaining products or services, please contact SynaptiCAD directly.
Library Information
SynaptiCAD's products work with Libero IDE and do not require any libraries. Appendix C in the SynaptiCAD help document describes how to setup the Libero IDE and SynaptiCAD's products so that they can properly call each other.
Contact Information
For additional information, contact SynaptiCAD at:SynaptiCAD Sales Inc.
605 Alleghany Street
Blacksburg, VA 24060
USA
Tel: +1 800.804.7073
+1 540.953.3390Fax: +1 540.953.3078
Email: sales@syncad.com
Web: www.syncad.com