Debug
Overview
Debug Tools
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Debug Info
Microsemi provides various debug tools to compliment design simulations and development by allowing verification and troubleshooting at the hardware level. After successful functional and post-layout simulations, Microsemi's design debug tools can help provide the designer with a pre-system level implementation early warning of other design issues.
Microsemi design debug focuses on analysis of the key elements of a flash design, such as embedded non-volatile memory (eNVM) data, SRAM data, Logic Elements, System Builder blocks.
Microsemi provided two debugging software tools for on-chip debugging – SmartDebug and Synopsys Identify ME.
SmartDebug
Microsemi SmartDebug tools help the designer to analyze the key elements of a flash design, such as the embedded non-volatile memory (eNVM) data, SRAM data, and probes capabilities. Microsemi PolarFire, SmartFusion2, IGLOO2 and RTG4 devices have built-in probe points that greatly enhance the ability to debug logic elements within the device. The enhanced debug features implemented in these devices give access to any logic element through Live Probe and Active Probe features, which enable designers to check the state of inputs and outputs in real-time, without any re-layout of the design.
- With Live Probe, two dedicated probes (one in RTG4) can be configured to observe a Probe Point which is any input or output of a logic element. The probe data can then be sent to an oscilloscope or even redirected back to the FPGA Fabric to drive a software logic analyzer.
- Active Probe allows dynamic asynchronous read and write to a flip-flop or probe point. This will enable a user to quickly observe the output of the logic internally or to quickly experiment on how the logic will be affected by writing to a probe point.
SmartDebug features can be accessed from within the Libero design flow or FlashPro software.
Identify ME
Identify is a third party chip debugging tool from Synopsys that allow you to debug your HDL design:
- In the target system
- At the target speed
- At the VHDL/Verilog RTL source level
The tool helps FPGA designer to quickly find and correct the functional design bugs by probing the internal signals of the design directly from the flash FPGA at system speed. The probed signals are inserted into the RTL and can be viewed directly as part of the RTL view for easy interpretation of the data. An advanced triggering mechanism focuses on a certain area of the design and sets breakpoints in RTL.
Key Features
- Automatically adds the debug logic to the design
- Trigger on an event, a series of events, pulse width, or an absence of an event after a period
- Trigger from one clock domain and trigger sampling in another domain
- Supports TCL-based command line interface that allows automation of instrumentation or debug using scripts
- Allows rapid debug of results and the ability to get useful data with less debug logic for heavily utilized FPGAs
- Remotely access and control FPGA hardware debug sessions over a network connection
There are three system components part of Identify
- Intelligent In Circuit Emulator (IICE)
- Identify Instrumentor
- Identify Debugger